W49F002U-12B Winbond Electronics, W49F002U-12B Datasheet - Page 6

• Manufacturer Part Number: W49F002U-12B
• Manufacturer: Winbond Electronics

Specifications of W49F002U-12B

• Density: 2Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 18b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PDIP
• Program/erase Volt (typ): 5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 50mA
• Mounting: Through Hole
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

W49F002U
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a
hardware reset occurs during the programming operation, the data at that particular location will be
corrupted.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot
be programmed back to a "1". Only erase operations can convert "0"s to "1"s.
Refer to the Embedded Programming Algorithm using typical command strings and bus operations.
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase
command.
Chip erase does not require the user to program the device prior to erase. Upon executing the
Embedded Erase Algorithm command sequence the device will automatically erase and verify the
entire memory for an all one data pattern. The erase is performed sequentially on each sector at the
same time (see "Feature"). The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Embedded Erase Algorithm using typical command strings and bus operations.
Sector Erase Command
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase
command. The sector address (any address location within the desired sector) is latched on the falling
edge of #WE, while the command (30H) is latched on the rising edge of #WE.
Sector erase does not require the user to program the device prior to erase.
When erasing a sector
or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the rising edge of the #WE pulse for the last sector erase
command pulse and terminates when the data on DQ7, Data Polling, is "1."
Refer to the Embedded Erase Algorithm using typical command strings and bus operations.
Write Operation Status
DQ7: Data Polling
The W49F002U device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt to read the device will produce the complement
of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce the true data last written to DQ7.
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7
output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce
a "1" at the DQ7 output.
The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm".
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