W49F002U-12B Winbond Electronics, W49F002U-12B Datasheet - Page 3

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W49F002U-12B

Manufacturer Part Number
W49F002U-12B
Description
Manufacturer
Winbond Electronics
Datasheet

Specifications of W49F002U-12B

Density
2Mb
Access Time (max)
120ns
Interface Type
Parallel
Boot Type
Top
Address Bus
18b
Operating Supply Voltage (typ)
5V
Operating Temp Range
0C to 70C
Package Type
PDIP
Program/erase Volt (typ)
5V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8b
Number Of Words
256K
Supply Current
50mA
Mounting
Through Hole
Pin Count
32
Lead Free Status / Rohs Status
Not Compliant

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FUNCTIONAL DESCRIPTION
Device Operation
Read Mode
The read operation of the W49F002U is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for details.
Write Mode
Device erase and program are accomplished via the command register. The content of the register
serves as inputs to the internal state machine. The state machine outputs dictate the function of the
device.
The command register itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information needed to execute the
command. The command register is written to bring #WE to logic low state when #CE is at logic low
state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.
Standby Mode
There are two ways to implement the standby mode on the W49F002U device, both using the #CE pin.
A CMOS standby mode is achieved with the
is typically reduced to less than 100 A. A TTL standby mode is achieved with the #CE pin held at V
Under this condition the current is typically reduced to less than 3 mA.
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
Output Disable Mode
With the #OE input at a logic high level (V
output pins to be in a high impedance state.
Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its
manufacturer and type. This mode is intended to be used by programming equipment for the purpose
of automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force V
Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from V
to V
hardware SID read function is not included in all parts; please refer to Ordering Information for
details.
IH
. All addresses are don t cares except A0 and A1 (see "Auto-select Codes"). Note: The
#CE input held at V
IH
), output from the device is disabled. This will cause the
- 3 -
DD
Publication Release Date: February 21, 2002
-0.3V. Under this condition the current
ID
(11.5V to 12.5V) on address pin A9.
W49F002U
Revision A6
IH
.
IL

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