W49F002U-12B

Manufacturer Part NumberW49F002U-12B
ManufacturerWinbond Electronics
W49F002U-12B datasheet
 


Specifications of W49F002U-12B

Density2MbAccess Time (max)120ns
Interface TypeParallelBoot TypeTop
Address Bus18bOperating Supply Voltage (typ)5V
Operating Temp Range0C to 70CPackage TypePDIP
Program/erase Volt (typ)5VSync/asyncAsynchronous
Operating Temperature ClassificationCommercialOperating Supply Voltage (min)4.5V
Operating Supply Voltage (max)5.5VWord Size8b
Number Of Words256KSupply Current50mA
MountingThrough HolePin Count32
Lead Free Status / Rohs StatusNot Compliant  
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The manufacturer and device codes may also be read via the command register; i.e., the W49F002U
is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in "Auto-select Codes".
Byte 0 (A0 = V
) represents the manufacturer s code (Winbond = DAh) and byte 1 (A0 = V
IL
device identifier code (W49F002U = 0Bh,). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be V
.
IL
Reset Mode: Hardware Reset
The #RESET pin provides a hardware method of resetting the device to reading array data. When the
system drives the #RESET pin low for at least a period of t
operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at V
enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode.
The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
Data Protection
The W49F002U is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from V
Low V
Inhibit
DD
To avoid initiation of a write cycle during V
when V
< 2.5V. The write and read operations are inhibited when V
DD
W49F002U ignores all write and read operations until V
control pins are in the correct logic state when V
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #OE, or #WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of #OE = V
#CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = V
edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
, the device immediately terminates any
RP
power-up and power-down transitions or system noise.
DD
power-up and power-down, the W49F002U locks out
DD
DD
> 2.5V. The user must ensure that the
DD
> 2.5V to prevent unintentional writes.
DD
, #CE = V
, or #WE = V
IL
IH
will not accept commands on the rising
IH
- 4 -
W49F002U
) the
IH
, the device
IL
is less than 2.5V typical. The
. To initiate a write cycle
IH