W49F002U-12B

Manufacturer Part NumberW49F002U-12B
ManufacturerWinbond Electronics
W49F002U-12B datasheet
 


Specifications of W49F002U-12B

Density2MbAccess Time (max)120ns
Interface TypeParallelBoot TypeTop
Address Bus18bOperating Supply Voltage (typ)5V
Operating Temp Range0C to 70CPackage TypePDIP
Program/erase Volt (typ)5VSync/asyncAsynchronous
Operating Temperature ClassificationCommercialOperating Supply Voltage (min)4.5V
Operating Supply Voltage (max)5.5VWord Size8b
Number Of Words256KSupply Current50mA
MountingThrough HolePin Count32
Lead Free Status / Rohs StatusNot Compliant  
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For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write
pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
#WE pulse.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while
the output enable (#OE) is asserted low. This means that the device is driving status information on
DQ7 at one instant of time and then that byte s valid data at the next instant of time. Depending on
when the system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 –
DQ6 may be still invalid. The valid data on DQ0
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm, or sector erase time-out (see "Command Definitions").
See " #DATA Polling During Embedded Algorithm Timing Diagrams".
DQ6: Toggle Bit
The W49F002U also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)
data from the device at any address will result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will
be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising
edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid
after the rising edge of the sixth #WE pulse in the six write pulse sequence. For Sector erase, the
Toggle Bit is valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active
during the sector erase time-out.
TABLE OF OPERATING MODES
Device Bus Operations
MODE
#CE
Read
Write
Write Inhibit
V
V
Standby
V
Output Disable
Reset
DQ7 will be read on the successive read attempts.
#OE
#WE
#RESET
V
V
V
V
IL
IL
IH
IH
V
V
V
V
IL
IH
IL
IH
X
V
X
IL
IH
X
X
V
IH
IH
X
X
V
IH
IH
V
V
V
V
IL
IH
IH
IH
X
X
X
V
IL
Publication Release Date: February 21, 2002
- 7 -
W49F002U
PIN
A0
A17
DQ0
DQ7
Ain
Dout
Ain
Din
X
High Z/DOUT
X
High Z/DOUT
X
High Z
X
High Z
X
High Z
Revision A6