K6T0808C1D-DB70 Samsung Semiconductor, K6T0808C1D-DB70 Datasheet - Page 7

• Manufacturer Part Number: K6T0808C1D-DB70
• Manufacturer: Samsung Semiconductor

Specifications of K6T0808C1D-DB70

• Density: 256Kb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 15b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 60mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

DATA RETENTION WAVE FORM
K6T0808C1D Family
CS controlled
TIMING WAVEFORM OF WRITE CYCLE(1)
TIMING WAVEFORM OF WRITE CYCLE(2)
Address
CS
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
2. t
3. t
4. t
V
4.5V
2.2V
V
CS
GND
Address
CS
WE
Data in
Data out
CC
DR
going low : A write end at the earliest transition among CS going high and WE going high, t
to the end of write.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the CS going low to the end of write.
is measured from the end or write to the address change. t
Data Undefined
High-Z
t
SDR
t
t
AS(3)
AS(3)
(CS Controlled)
(WE Controlled)
WR
Data Retention Mode
t
WHZ
t
AW
applied in case a write ends as CS or WE going high.
t
CS V
AW
t
t
WC
CW(2)
t
t
CW(2)
WC
t
CC
t
WP(1)
WP(1)
- 0.2V
t
t
DW
DW
Data Valid
Data Valid
WP
is measured from the begining of write
t
t
WR(4)
WR(4)
t
t
DH
DH
t
OW
High-Z
t
RDR
CMOS SRAM
November 1997
Revision 1.01