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MC68HC705C8ACB
MC68HC705C8ACB | |
|---|---|
| Manufacturer Part Number | MC68HC705C8ACB |
| Manufacturer | Freescale Semiconductor |
| MC68HC705C8ACB datasheets |
|
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Warranty: 60 days
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Specifications of MC68HC705C8ACB | |||
|---|---|---|---|
| Cpu Family | HC05 | Device Core Size | 8b |
| Frequency (max) | 2.1MHz | Interface Type | SCI/SPI |
| Program Memory Type | EPROM | Program Memory Size | 8KB |
| Total Internal Ram Size | 304Byte | # I/os (max) | 24 |
| Number Of Timers - General Purpose | 1 | Operating Supply Voltage (typ) | 3.3/5V |
| Operating Supply Voltage (max) | 5.5V | Operating Supply Voltage (min) | 3V |
| Instruction Set Architecture | CISC | Operating Temp Range | -40C to 85C |
| Operating Temperature Classification | Industrial | Mounting | Through Hole |
| Pin Count | 42 | Package Type | SPDIP |
| Lead Free Status / Rohs Status | Not Compliant | ||
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PrevNext
Freescale Semiconductor, Inc.
3.3.5 Condition Code Register
The condition code register (CCR) shown in
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four bits that
indicate the results of prior instructions.
Read:
Write:
Reset:
H — Half-Carry Bit
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
affect on the half-carry flag.
I — Interrupt Mask Bit
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a CLI,
STOP, or WAIT instruction.
MC68HC705C8A — Rev. 3
MOTOROLA
For More Information On This Product,
Bit 7
6
5
4
1
1
1
H
1
1
1
U
= Unimplemented
Figure 3-6. Condition Code Register (CCR)
Central Processor Unit (CPU)
Go to: www.freescale.com
Central Processor Unit (CPU)
CPU Registers
Figure 3-6
is an 8-bit
3
2
1
Bit 0
I
N
Z
C
1
U
U
U
U = Unaffected
Technical Data
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