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MC68HC705C8ACB
MC68HC705C8ACB | |
|---|---|
| Manufacturer Part Number | MC68HC705C8ACB |
| Manufacturer | Freescale Semiconductor |
| MC68HC705C8ACB datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of MC68HC705C8ACB | |||
|---|---|---|---|
| Cpu Family | HC05 | Device Core Size | 8b |
| Frequency (max) | 2.1MHz | Interface Type | SCI/SPI |
| Program Memory Type | EPROM | Program Memory Size | 8KB |
| Total Internal Ram Size | 304Byte | # I/os (max) | 24 |
| Number Of Timers - General Purpose | 1 | Operating Supply Voltage (typ) | 3.3/5V |
| Operating Supply Voltage (max) | 5.5V | Operating Supply Voltage (min) | 3V |
| Instruction Set Architecture | CISC | Operating Temp Range | -40C to 85C |
| Operating Temperature Classification | Industrial | Mounting | Through Hole |
| Pin Count | 42 | Package Type | SPDIP |
| Lead Free Status / Rohs Status | Not Compliant | ||
PrevNext
Freescale Semiconductor, Inc.
Resets
Address:
Read:
Write:
Reset:
Figure 5-2. Programmable COP Reset Register (COPRST)
The programmable COP control register (COPCR) shown in
does these functions:
•
•
•
•
Address:
Read:
Write:
Reset:
Figure 5-3. Programmable COP Control Register (COPCR)
COPF — COP Flag
This read-only bit is set when a timeout of the programmable COP
watchdog occurs or when the clock monitor detects a slow or absent
internal clock. Clear the COPF bit by reading the COP control register.
Reset has no effect on the COPF bit.
Technical Data
64
$001D
Bit 7
6
5
Bit 7
6
5
U
U
U
= Unimplemented
Flags programmable COP watchdog resets
Enables the clock monitor
Enables the programmable COP watchdog
Controls the timeout period of the programmable COP watchdog
$001E
Bit 7
6
5
0
0
0
COPF
0
0
0
= Unimplemented
1 = COP timeout or internal clock failure
0 = No COP timeout and no internal clock failure
Resets
For More Information On This Product,
Go to: www.freescale.com
4
3
2
1
4
3
2
1
U
U
U
U
U = Unaffected
Figure 5-3
4
3
2
1
CME
PCOPE
CM1
U
0
0
0
U = Unaffected
MC68HC705C8A — Rev. 3
Bit 0
Bit 0
U
Bit 0
CM0
0
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