MC68HC711E9FU

Manufacturer Part NumberMC68HC711E9FU
ManufacturerFreescale Semiconductor
MC68HC711E9FU datasheet
 

Specifications of MC68HC711E9FU

Cpu FamilyHC11Device Core Size8b
Frequency (max)4MHzInterface TypeSCI/SPI
Program Memory TypeEPROMProgram Memory Size12KB
Total Internal Ram Size512Byte# I/os (max)38
Number Of Timers - General Purpose8Operating Supply Voltage (typ)3.3/5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)3V
On-chip Adc8-chx8-bitInstruction Set ArchitectureCISC
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count64
Package TypePQFPLead Free Status / Rohs StatusNot Compliant
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9.7.1 Pulse Accumulator Control Register
Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either the OC5
function or the IC4 function, while two other bits select the rate for the real-time interrupt system.
Address:
$1026
Bit 7
Read:
DDRA7
Write:
Reset:
0
Figure 9-25. Pulse Accumulator Control Register (PACTL)
DDRA7 — Data Direction for Port A Bit 7
Refer to
Chapter 6 Parallel Input/Output (I/O)
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control Bit
This bit has different meanings depending on the state of the PAMOD bit, as shown in
Table 9-7. Pulse Accumulator Edge Control
PAMOD
0
0
1
1
DDRA3 — Data Direction for Port A Bit 3
Refer to
Chapter 6 Parallel Input/Output (I/O)
I4/O5 — Input Capture 4/Output Compare 5 Bit
0 = Output compare 5 function enable (no IC4)
1 = Input capture 4 function enable (no OC5)
RTR[1:0] — RTI Interrupt Rate Select Bits
Refer to
9.5 Real-Time Interrupt
Freescale Semiconductor
6
5
4
3
PAEN
PAMOD
PEDGE
DDRA3
0
0
0
0
Ports.
PEDGE
Action on Clock
0
PAI falling edge increments the counter.
1
PAI rising edge increments the counter.
0
A 0 on PAI inhibits counting.
1
A 1 on PAI inhibits counting.
Ports.
(RTI).
M68HC11E Family Data Sheet, Rev. 5.1
Pulse Accumulator
2
1
Bit 0
I4/O5
RTR1
RTR0
0
0
0
Table
9-7.
145