MC68HC711E9FU

Manufacturer Part NumberMC68HC711E9FU
ManufacturerFreescale Semiconductor
MC68HC711E9FU datasheet
 

Specifications of MC68HC711E9FU

Cpu FamilyHC11Device Core Size8b
Frequency (max)4MHzInterface TypeSCI/SPI
Program Memory TypeEPROMProgram Memory Size12KB
Total Internal Ram Size512Byte# I/os (max)38
Number Of Timers - General Purpose8Operating Supply Voltage (typ)3.3/5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)3V
On-chip Adc8-chx8-bitInstruction Set ArchitectureCISC
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count64
Package TypePQFPLead Free Status / Rohs StatusNot Compliant
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Operating Modes and On-Chip Memory
Address:
$103F
Bit 7
Read:
EE3
Write:
Resets:
Single chip:
1
Bootstrap:
1
Expanded:
U
Test:
U
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,
but the function of COP is controlled by the DISR bit in TEST1 register.
Figure 2-11. MC68HC811E2 System Configuration Register (CONFIG)
EE[3:0] — EEPROM Mapping Bits
EE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to be remapped to any
4-Kbyte boundary. See
Table
44
6
5
4
3
EE2
EE1
EE0
NOSEC
1
1
1
U
1
1
1
U
U
U
U
1
U
U
U
1
= Unimplemented
2-3.
Table 2-3. EEPROM Mapping
EE[3:0]
EEPROM Location
0 0 0 0
$0800–$0FFF
0 0 0 1
$1800–$1FFF
0 0 1 0
$2800–$2FFF
0 0 1 1
$3800–$3FFF
0 1 0 0
$4800–$4FFF
0 1 0 1
$5800–$5FFF
0 1 1 0
$6800–$6FFF
0 1 1 1
$7800–$7FFF
1 0 0 0
$8800–$8FFF
1 0 0 1
$9800–$9FFF
1 0 1 0
$A800–$AFFF
1 0 1 1
$B800–$BFFF
1 1 0 0
$C800–$CFFF
1 1 0 1
$D800–$DFFF
1 1 1 0
$E800–$EFFF
1 1 1 1
$F800–$FFFF
M68HC11E Family Data Sheet, Rev. 5.1
2
1
Bit 0
NOCOP
EEON
U
1
1
U(L)
1
1
U
1
U
U(L)
1
0
Freescale Semiconductor