MC68HC711E9FU

Manufacturer Part NumberMC68HC711E9FU
ManufacturerFreescale Semiconductor
MC68HC711E9FU datasheet
 


Specifications of MC68HC711E9FU

Cpu FamilyHC11Device Core Size8b
Frequency (max)4MHzInterface TypeSCI/SPI
Program Memory TypeEPROMProgram Memory Size12KB
Total Internal Ram Size512Byte# I/os (max)38
Number Of Timers - General Purpose8Operating Supply Voltage (typ)3.3/5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)3V
On-chip Adc8-chx8-bitInstruction Set ArchitectureCISC
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count64
Package TypePQFPLead Free Status / Rohs StatusNot Compliant
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3.4 Conversion Process
The A/D conversion sequence begins one E-clock cycle after a write to the A/D control/status register,
ADCTL. The bits in ADCTL select the channel and the mode of conversion.
An input voltage equal to V
converts to $00 and an input voltage equal to V
RL
scale), with no overflow indication. For ratiometric conversions of this type, the source of each analog
input should use V
as the supply voltage and be referenced to V
RH
3.5 Channel Assignments
The multiplexer allows the A/D converter to select one of 16 analog signals. Eight of these channels
correspond to port E input lines to the MCU, four of the channels are internal reference points or test
functions, and four channels are reserved. Refer to
Table 3-1. Converter Channel Assignments
Channel
Number
9 – 12
1. Used for factory testing
3.6 Single-Channel Operation
The two types of single-channel operation are:
1. When SCAN = 0, the single selected channel is converted four consecutive times. The first result
is stored in A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourth
conversion is complete, all conversion activity is halted until a new conversion command is written
to the ADCTL register.
2. When SCAN = 1, conversions continue to be performed on the selected channel with the fifth
conversion being stored in register ADR1 (overwriting the first conversion result), the sixth
conversion overwriting ADR2, and so on.
Freescale Semiconductor
Table
3-1.
Channel
Signal
1
AN0
2
AN1
3
AN2
4
AN3
5
AN4
6
AN5
7
AN6
8
AN7
Reserved
(1)
13
V
RH
(1)
14
V
RL
(1)
15
(V
)/2
RH
(1)
16
Reserved
M68HC11E Family Data Sheet, Rev. 5.1
Conversion Process
converts to $FF (full
RH
.
RL
Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
61