MC68HC711E9FU Freescale Semiconductor, MC68HC711E9FU Datasheet - Page 66

• Manufacturer Part Number: MC68HC711E9FU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711E9FU

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 12KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 38
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

4.2.1 Accumulators A, B, and D
Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic
calculations or data manipulations. For some instructions, these two accumulators are treated as a single
double-byte (16-bit) accumulator called accumulator D. Although most instructions can use accumulators
A or B interchangeably, these exceptions apply:
4.2.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an
instruction to create an effective address. The IX register can also be used as a counter or as a temporary
storage register.
4.2.3 Index Register Y (IY)
The 16-bit IY register performs an indexed mode function similar to that of the IX register. However, most
instructions using the IY register require an extra byte of machine code and an extra cycle of execution
time because of the way the opcode map is implemented. Refer to
information.
4.2.4 Stack Pointer (SP)
The M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the address
space and can be any size up to the amount of memory available in the system. Normally, the SP is
initialized by one of the first instructions in an application program. The stack is configured as a data
structure that grows downward from high memory to low memory. Each time a new byte is pushed onto
the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. At
any given time, the SP holds the 16-bit address of the next free location in the stack.
summary of SP operations.
When a subroutine is called by a jump-to-subroutine (JSR) or branch-to- subroutine (BSR) instruction, the
address of the instruction after the JSR or BSR is automatically pushed onto the stack, least significant
byte first. When the subroutine is finished, a return-from-subroutine (RTS) instruction is executed. The
RTS pulls the previously stacked return address from the stack and loads it into the program counter.
Execution then continues at this recovered return address.
When an interrupt is recognized, the current instruction finishes normally, the return address (the current
value in the program counter) is pushed onto the stack, all of the CPU registers are pushed onto the stack,
and execution continues at the address specified by the vector for the interrupt.
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Central Processor Unit (CPU)
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The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents of 16-bit
register X or Y, but there are no equivalent instructions that use A instead of B.
The TAP and TPA instructions transfer data from accumulator A to the condition code register or
from the condition code register to accumulator A. However, there are no equivalent instructions
that use B rather than A.
The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD)
arithmetic operations, but there is no equivalent BCD instruction to adjust accumulator B.
The add, subtract, and compare instructions associated with both A and B (ABA, SBA, and CBA)
only operate in one direction, making it important to plan ahead to ensure that the correct operand
is in the correct accumulator.
M68HC11E Family Data Sheet, Rev. 5.1
4.4 Opcodes and Operands
Freescale Semiconductor
Figure 4-2
for further
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