MC68HC711E9FU Freescale Semiconductor, MC68HC711E9FU Datasheet - Page 77

• Manufacturer Part Number: MC68HC711E9FU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711E9FU

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 12KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 38
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
SBCA (opr)
SBCB (opr)
SUBA (opr)
SUBB (opr)
SUBD (opr)
Mnemonic
STAA (opr)
STAB (opr)
STX (opr)
STD (opr)
STS (opr)
STY (opr)
TST (opr)
STOP
TEST
SEC
SEV
SWI
TAB
TAP
TBA
TPA
SEI
Test for Zero or
Transfer A to B
Transfer B to A
TEST (Only in
Memory from
Memory from
Memory from
Subtract with
Carry from A
Subtract with
Carry from B
Set Overflow
Stop Internal
Transfer A to
Register to A
Set Interrupt
Accumulator
Accumulator
Accumulator
Test Modes)
CC Register
Transfer CC
Store Stack
Store Index
Store Index
Operation
Register X
Register Y
Set Carry
Software
Subtract
Subtract
Subtract
Interrupt
Pointer
Clocks
Minus
Mask
Store
Store
Store
Flag
D
D
A
B
A
B
Address Bus Counts
A ⇒ M, B ⇒ M + 1
D – M : M + 1 ⇒ D
SP ⇒ M : M + 1
See Figure 3–2
A – M – C ⇒ A
B – M – C ⇒ B
IX ⇒ M : M + 1
IY ⇒ M : M + 1
Description
A – M ⇒ A
B – M ⇒ B
A ⇒ CCR
CCR ⇒ A
A ⇒ M
B ⇒ M
1 ⇒ C
1 ⇒ V
A ⇒ B
B ⇒ A
M – 0
1 ⇒ I
—
Table 4-2. Instruction Set (Sheet 6 of 7)
M68HC11E Family Data Sheet, Rev. 5.1
A
A
A
A
A
B
B
B
B
B
A
A
A
A
B
B
B
B
A
A
A
A
A
A
A
A
A
A
Addressing
Mode
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
INH
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
INH
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
INH
EXT
IND,X
IND,Y
18
18
18
18
18
18
CD
18
18
1A
18
18
18
18
18
Opcode
06
00
82
92
A2
A2
C2
D2
E2
E2
0D
0F
0B
97
B7
D7
F7
DD
FD
CF
9F
BF
DF
FF
DF
FF
EF
EF
80
90
A0
A0
C0
D0
E0
E0
83
93
A3
A3
3F
16
17
07
7D
6D
6D
B2
F2
A7
A7
E7
E7
ED
ED
AF
AF
EF
EF
B0
F0
B3
Instruction
ii
dd
hh
ff
ff
ii
dd
hh
ff
ff
dd
hh
ff
ff
dd
hh
ff
ff
dd
hh
ff
ff
dd
hh
ff
ff
dd
hh
ff
ff
dd
hh
ff
ff
ii
dd
hh
ff
ff
ii
dd
hh
ff
ff
jj
dd
hh
ff
ff
hh
ff
ff
Operand
—
—
—
—
—
—
—
—
—
—
ll
ll
ll
ll
ll
ll
ll
ll
ll
ll
kk
ll
ll
Cycles
14
2
3
4
4
5
2
3
4
4
5
2
2
2
3
4
4
5
3
4
4
5
4
5
5
6
2
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
2
2
2
6
6
7
*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
∆
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
↓
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H
∆
Condition Codes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
∆
I
—
—
—
—
—
—
—
N
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Instruction Set
—
—
—
—
—
—
—
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
—
—
—
V
∆
∆
∆
∆
∆
∆
1
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C
∆
∆
∆
∆
∆
∆
1
0
77