MC68HC11E1CFN3R2 Freescale Semiconductor, MC68HC11E1CFN3R2 Datasheet - Page 109

• Manufacturer Part Number: MC68HC11E1CFN3R2
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC11E1CFN3R2

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 3MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 38
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

7.5.2 Address-Mark Wakeup
The serial characters in this type of wakeup consist of seven (eight if M = 1) information bits and an MSB,
which indicates an address character (when set to 1, or mark). The first character of each message is an
addressing character (MSB = 1). All receivers in the system evaluate this character to determine if the
remainder of the message is directed toward this particular receiver. As soon as a receiver determines
that a message is not intended for it, the receiver activates the RWU function by using a software write to
set the RWU bit. Because setting RWU inhibits receiver-related flags, there is no further software
overhead for the rest of this message.
When the next message begins, its first character has its MSB set, which automatically clears the RWU
bit and enables normal character reception. The first character whose MSB is set is also the first character
to be received after wakeup because RWU gets cleared before the stop bit for that frame is serially
received. This type of wakeup allows messages to include gaps of idle time, unlike the idle-line method,
but there is a loss of efficiency because of the extra bit time for each character (address bit) required for
all characters.
7.6 SCI Error Detection
Three error conditions – SCDR overrun, received bit noise, and framing – can occur during generation of
SCI system interrupts. Three bits (OR, NF, and FE) in the serial communications status register (SCSR)
indicate if one of these error conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be transferred from the receive shift
register to the SCDR and the SCDR is already full (RDRF bit is set). When an overrun error occurs, the
data that caused the overrun is lost and the data that was already in SCDR is not disturbed. The OR is
cleared when the SCSR is read (with OR set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and stop bits.
The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is read (with FE
equal to 1) followed by a read of the SCDR.
When no stop bit is detected in the received data character, the framing error (FE) bit is set. FE is set at
the same time as the RDRF. If the byte received causes both framing and overrun errors, the processor
only recognizes the overrun error. The framing error flag inhibits further transfer of data into the SCDR
until it is cleared. The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of
the SCDR.
7.7 SCI Registers
Five addressable registers are associated with the SCI:
The SCI registers are the same for all M68HC11 E-series devices with one exception. The SCI system
for MC68HC(7)11E20 contains an extra bit in the BAUD register that provides a greater selection of baud
prescaler rates. Refer to
Freescale Semiconductor
•
•
Four control and status registers:
–
–
–
–
One data register:
–
Serial communications control register 1 (SCCR1)
Serial communications control register 2 (SCCR2)
Baud rate register (BAUD)
Serial communications status register (SCSR)
Serial communications data register (SCDR)
7.7.5 Baud Rate
M68HC11E Family Data Sheet, Rev. 5.1
Register,
Figure
7-8, and
Figure
7-9.
SCI Error Detection
109