MC68HC11E1CFN3R2 Freescale Semiconductor, MC68HC11E1CFN3R2 Datasheet - Page 132
MC68HC11E1CFN3R2
Manufacturer Part Number
MC68HC11E1CFN3R2
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC11E1CFN3R2.pdf
(242 pages)
Specifications of MC68HC11E1CFN3R2
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
3MHz
Interface Type
SCI/SPI
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
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Timing Systems
input capture register pair inhibits a new capture transfer for one bus cycle. If a double-byte read
instruction, such as load double accumulator D (LDD), is used to read the captured value, coherency is
assured. When a new input capture occurs immediately after a high-order byte read, transfer is delayed
for an additional cycle but the value is not lost.
132
Register name: Timer Input Capture 1 Register (High)
Register name: Timer Input Capture 1 Register (Low)
Register name: Timer Input Capture 2 Register (High)
Register name: Timer Input Capture 2 Register (Low)
Register name: Timer Input Capture 3 Register (High)
Register name: Timer Input Capture 3 Register (Low)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Bit 15
Bit 15
Bit 15
Figure 9-4. Timer Input Capture 1 Register Pair (TIC1)
Figure 9-5. Timer Input Capture 2 Register Pair (TIC2)
Figure 9-6. Timer Input Capture 3 Register Pair (TIC3)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 14
Bit 14
Bit 14
Bit 6
Bit 6
Bit 6
6
6
6
6
6
6
M68HC11E Family Data Sheet, Rev. 5.1
Bit 13
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
5
5
5
5
5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Bit 12
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
Address: $1011
Address: $1013
Address: $1015
Address: $1010
Address: $1012
Address: $1014
4
4
4
4
4
4
Bit 11
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
3
3
3
3
3
3
Bit 10
Bit 10
Bit 10
Bit 2
Bit 2
Bit 2
2
2
2
2
2
2
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
1
1
1
1
1
1
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
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