MC68HC11E1CFN3R2 Freescale Semiconductor, MC68HC11E1CFN3R2 Datasheet - Page 165

• Manufacturer Part Number: MC68HC11E1CFN3R2
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC11E1CFN3R2

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 3MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 38
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
PORT C (OUT)
Notes:
PORT C (OUT)
NOTES:
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRB (IN)
STRA (IN)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRA (IN)
Notes:
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
NOTES:
Figure 10-13. 3-State Variation of Output Handshake Timing Diagram
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRA (IN)
STRA (IN)
E
(DDR = 1)
STRA (IN)
(DDR = 0)
STRA (IN)
(DDR = 0)
E
DDR = 1
DDR = 0
DDR = 0
PREVIOUS PORT DATA
PREVIOUS PORT DATA
Figure 10-12. Port C Output Handshake Timing Diagram
E
E
b) STRA ACTIVE AFTER PORTCL WRITE
a) STRA ACTIVE BEFORE PORTCL WRITE
b) STRA ACTIVE AFTER PORTCL WRITE
a) STRA ACTIVE BEFORE PORTCL WRITE
WRITE PORTCL
READ PORTCL
WRITE PORTCL
READ PORTCL
OLD DATA
t
t
OLD DATA
PCD
PCD
M68HC11E Family Data Sheet, Rev. 5.1
(STRA Enables Output Buffer)
t
(1)
t
1
PWD
t
PWD
(1)
1
t
PWD
PWD
NEW DATA VALID
NEW DATA VALID
t
t
DEB
DEB
NEW DATA VALID
NEW DATA VALID
t
t
DEB
DEB
t
t
PCD
PCD
"READY"
“READY”
NEW DATA VALID
t
t
AES
AES
NEW DATA VALID
“READY”
"READY"
MC68L11E9/E20 Peripheral Port Timing
t
t
t
t
t
PCH
PCH
PCH
PCH
PCH
t
t
DEB
t
DEB
t
t
AES
t
t
t
AES
PCZ
PCZ
PCZ
PCZ
PORT C OUTPUT HNDSHK TIM
t
t
DEB
DEB
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