MC68HC11E1CFN3R2 Freescale Semiconductor, MC68HC11E1CFN3R2 Datasheet - Page 83

• Manufacturer Part Number: MC68HC11E1CFN3R2
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC11E1CFN3R2

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 3MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 38
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

5.2.6 Configuration Control Register
EE[3:0] — EEPROM Mapping Bits
NOSEC — Security Mode Disable Bit
NOCOP — COP System Disable Bit
ROMON — ROM (EPROM) Enable Bit
EEON — EEPROM Enable Bit
5.3 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced to an initial state.
Depending on the cause of the reset and the operating mode, the reset vector can be fetched from any
of six possible locations. Refer to
These initial states then control on-chip peripheral systems to force them to known startup states, as
described in the following subsections.
5.3.1 Central Processor Unit (CPU)
After reset, the central processor unit (CPU) fetches the restart vector from the appropriate address during
the first three cycles and begins executing instructions. The stack pointer and other CPU registers are
indeterminate immediately after reset; however, the X and I interrupt mask bits in the condition code
register (CCR) are set to mask any interrupt requests. Also, the S bit in the CCR is set to inhibit stop mode.
Freescale Semiconductor
EE[3:0] apply only to MC68HC811E2. Refer to
Refer to
Refer to
Refer to
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
Chapter 2 Operating Modes and On-Chip
Chapter 2 Operating Modes and On-Chip
Chapter 2 Operating Modes and On-Chip
Address:
Reset:
Read:
Write:
COP Watchdog Timeout
Table 5-2. Reset Cause, Reset Vector, and Operating Mode
Clock monitor failure
POR or RESET pin
Cause of Reset
$103F
Bit 7
EE3
Figure 5-3. Configuration Control Register (CONFIG)
0
EE2
0
6
Table
M68HC11E Family Data Sheet, Rev. 5.1
5-2.
EE1
5
0
Normal Mode
$FFFC, FFFD
$FFFE, FFFF
$FFFA, FFFB
Vector
Chapter 2 Operating Modes and On-Chip
EE0
4
0
Memory.
Memory.
Memory.
NOSEC
3
1
NOCOP
$BFFC, $BFFD
$BFFE, $BFFF
$BFFA, $BFFB
or Bootstrap
Special Test
2
1
ROMON
1
1
EEON
Bit 0
1
Effects of Reset
Memory.
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