MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet
MC68HC908LD60IFU
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MC68HC908LD60IFU Summary of contents
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MC68HC908LD60 Technical Data M68HC08 Microcontrollers Rev. 1.1 MC68HC908LD60/D August 16, 2005 freescale.com ...
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... Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc Equal Opportunity/Affirmative Action Employer. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Technical Data © Freescale, Inc., 2001 Technical Data 3 ...
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... Technical Data Technical Data 4 MC68HC908LD60 Technical Data Rev. 1.1 — Freescale Semiconductor ...
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... Section 19. Keyboard Interrupt Module (KBI 257 Section 20. Computer Operating Properly (COP 265 Section 21. Break Module (BRK 271 Section 22. Electrical Specifications 279 Section 23. Mechanical Specifications . . . . . . . . . . . . . 287 Section 24. Ordering Information . . . . . . . . . . . . . . . . . 289 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor List of Sections List of Sections Technical Data 5 ...
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... List of Sections Technical Data 6 MC68HC908LD60 List of Sections Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Section 2. Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 39 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input/Output (I/O) Section Section 3 ...
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... Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table of Contents MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Section 7. Oscillator (OSC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2 Oscillator Enable Signal (SIMOSCEN External Clock Source (OSCXCLK) ...
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... Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .116 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 116 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 116 SIM Counter and Reset States 117 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table of Contents MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor SWI Instruction 121 Interrupt Status Registers 121 Interrupt Status Register 123 Interrupt Status Register 123 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 124 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Wait Mode ...
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... TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 154 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Section 12. Pulse Width Modulator (PWM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 PWM Registers 167 PWM Data Registers (0PWM–7PWM 167 PWM Control Register (PWMCR 168 Table of Contents MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 13. Analog-to-Digital Converter (ADC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Interrupts ...
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... DDC Data Transmit Register (DDTR 206 DDC Data Receive Register (DDRR 207 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 208 Section 16. Sync Processor Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table of Contents MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Hsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 216 Vsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 216 Composite Sync Polarity Detection . . . . . . . . . . . . . . . . 216 Sync Signal Counters 217 Polarity Controlled HOUT and VOUT Outputs . . . . . . . . . . 217 Clamp Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Low Vertical Frequency Detect . . . . . . . . . . . . . . . . . . . . . 219 Sync Processor I/O Registers 219 Sync Processor Control & ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 Keyboard Initialization 261 I/O Registers 261 Keyboard Status and Control Register 262 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 263 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 264 Table of Contents MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 20. Computer Operating Properly (COP) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 Power-On Reset 267 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Reset Vector Fetch ...
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... Functional Operating Range 281 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 282 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 283 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Section 23. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 64-Pin Plastic Quad Flat Pack (QFP 288 Table of Contents MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 24. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Table of Contents Table of Contents Technical Data 19 ...
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... Table of Contents Technical Data 20 Table of Contents MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Title MC68HC908LD60 MCU Block Diagram 64-Pin QFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .43 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 56 47,616-byte FLASH Control Register (FLCR 13k-byte FLASH Control Register (FLCR1 13k-Byte FLASH Even Byte Write Buffer (13KEBUF) ...
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... SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SIM I/O Register Summary .110 OSC Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 List of Figures Page MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... DDC Status Register (DSR 204 15-7 DDC Data Transmit Register (DDTR 206 15-8 DDC Data Receive Register (DDRR 207 15-9 Data Transfer Sequences for Master/Slave MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Title Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 209 List of Figures List of Figures Page ...
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... Data Direction Register E (DDRE 249 17-19 Port E I/O Circuit 250 18-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18-2 IRQ I/O Register Summary .253 18-3 IRQ Status and Control Register (INTSCR 255 Technical Data 24 Title MC68HC908LD60 List of Figures Page Rev. 1.1 — Freescale Semiconductor ...
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... SIM Break Status Register (SBSR 277 21-7 SIM Break Flag Control Register (SBFCR 278 22-1 MMIIC Signal Timings 285 23-1 64-Pin Plastic Quad Flat Pack (QFP 288 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Title List of Figures List of Figures Page Technical Data 25 ...
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... List of Figures Technical Data 26 MC68HC908LD60 List of Figures Rev. 1.1 — Freescale Semiconductor ...
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... Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 141 11-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11-2 Prescaler Selection 157 11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 161 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Title Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 FLASH Memory Array Summary . . . . . . . . . . . . . . . . . . . . . . . 56 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Free-Running HSOUT, VSOUT, DE, and DCLK Settings ...
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... Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 22-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 280 22-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 22-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 22-4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 282 22-5 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22-6 TIM Characteristics 283 Technical Data 28 Title MC68HC908LD60 List of Tables Page Rev. 1.1 — Freescale Semiconductor ...
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... Sync Processor Timing 284 22-10 DDC12AB/MMIIC Interface Input Signal Timing 285 22-11 DDC12AB/MMIIC Interface Output Signal Timing . . . . . . . . . 285 22-12 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . . 286 24-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Title List of Tables List of Tables Page Technical Data 29 ...
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... List of Tables Technical Data 30 MC68HC908LD60 List of Tables Rev. 1.1 — Freescale Semiconductor ...
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... With special modules such as the sync processor, analog-to-digital converter, pulse modulator module, DDC12AB interface, and multi- master IIC interface, the MC68HC908LD60 is designed specifically for use in digital monitor systems. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 ...
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... CLAMP pulse output to the external pre-amp chip 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 32 sync or composite sync inputs General Description 1 feature MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... DDC is a VESA bus standard. 2. IIC is a proprietary Philips interface bus. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 1 DDC12AB module with the following: – DDC1 hardware 2 – Multi-master IIC hardware for DDC2AB; with dual address Additional multi-master IIC module ...
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... Pin is +5V input General Description PTA7/KBI7 : PTA0/KBI0 PTB7/PWM7 : PTB0/PWM0 PTC6 PTC5/ADC5 : PTC0/ADC0 HSYNC†† VSYNC†† CLAMP/TCH0 PTD7/IICSDA† PTD6/IICSCL† PTD5/DDCSDA† PTD4/DDCSCL† PTD3/HOUT PTD2/VOUT PTD1/DE PTD0/DCLK PTE7 : PTE0 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... PTE1 9 PTE2 10 PTE3 11 PTE4 12 PTE5 13 PTE6 14 PTE7 15 CGMXFC 16 RESERVED pins should not be connected. Figure 1-2. 64-Pin QFP Pin Assignment MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor General Description General Description Pin Assignments PTA3/KBI3 48 PTA2/KBI2 47 PTA1/KBI1 46 PTA0/KBI0 45 VDD2 44 PTB7/PWM7 43 PTB6/PWM6 42 PTB5/PWM5 41 PTB4/PWM4 40 PTB3/PWM3 ...
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... Each pin contains a pullup device to VDD when it is configured as an external keyboard interrupt pin. See Section 17. Input/Output (I/O) Ports Section 19. Keyboard Interrupt Module General Description Table 1-1. PIN DESCRIPTION (OSC). and (SIM). (CGM). Processor. Processor. and (KBI). MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... PTB7/PWM7–PTB0/PWM0 PTC5/ADC5–PTC0/ADC0 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Table 1-1. Pin Functions (Continued) PIN NAME These are shared-function, bidirectional I/O port pins. Each pin can be configured as a standard I/O pin or a PWM output channel. See Section 17. Input/Output (I/O) Ports Section 12 ...
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... Section 11. Timer Interface Module (TIM) and Section 16. Sync These are bidirectional I/O port pins. PTE7–PTE0 See Section 17. Input/Output (I/ Although the I/O ports of the MC68HC908LD60 do not DD SS General Description PIN DESCRIPTION and Processor. Processor. Ports. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure locations are shaded. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 39 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input/Output (I/O) Section Figure 2-1, includes: ...
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... Break status and control register, BRKSCR • $FE0F; Reserved • $FFFF; COP control register, COPCTL Data registers are shown in locations. Technical Data 40 Figure 2-1 and in register figures in this document, Figure 2-2. Table 2-1 MC68HC908LD60 Memory Map is a list of vector Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $0000 I/O Registers ↓ 128 Bytes $007F $0080 ↓ 1,024 Bytes $047F $0480 Unimplemented ↓ 896 Bytes $07FF $0800 ↓ 1,024 Bytes $0BFF $0C00 FLASH Memory ↓ 1,024 Bytes (8 × 128-Byte Blocks) $0FFF $1000 FLASH Memory ↓ ...
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... Break Address Register Low (BRKL) $FE0E Break Status and Control Register (BRKSCR) $FE0F Reserved $FE10 Monitor ROM ↓ 464 Bytes $FFDF $FFE0 FLASH Vectors ↓ 32 Bytes $FFFF Figure 2-1. Memory Map (Continued) Memory Map MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... Write: (PTE) Reset: Read: Data Direction Register E $0009 Write: (DDRE) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset 0 PTC6 ...
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... PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX Reserved MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... DDC2 Address Register $001C Write: (D2ADR) Reset: Read: $001D Unimplemented Write: Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit Bit15 Bit14 Bit13 Bit12 Indeterminate after reset Bit7 Bit6 Bit5 Indeterminate after reset ALIF NAKIF ...
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... AD7 AD6 AD5 AD4 Unaffected after Reset 0 ADIV2 ADIV1 ADIV0 Unimplemented Memory Map Bit 0 IRQF 0 IMASK MODE ACK SSREC COPRS STOP COPD VRS7 VRS6 VRS5 VRS4 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 Reserved MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
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... Reserved Write: $004D Reset: Read: Keyboard Status and $004E Control Register Write: (KBSCR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit DCLKPH1 DCLKPH0 VSIF VSIE VEDGE COMP VOF 0 0 VF12 CPW1 ...
Page 48
... MMTD7 MMTD6 MMTD5 MMTD4 Unimplemented Memory Map Bit 0 KBIE3 KBIE2 KBIE1 KBIE0 Bit3 Bit2 Bit1 Bit0 VOUTE DEE DCLKE MMRW MMBR2 MMBR1 MMBR0 MMAD3 MMAD2 MMAD1 MMEXTAD MMTXAK MMTXBE MMRXBF MMTD3 MMTD2 MMTD1 MMTD0 Reserved MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 49
... Reset: Read: PWM7 Data Register $0077 Write: (7PWM) Reset: Read: PWM Control Register $0078 Write: (PWMCR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit MMRD6 MMRD5 MMRD4 0PWM4 0PWM3 0PWM2 0PWM1 1PWM4 ...
Page 50
... Figure 2-2. Control, Status, and Data Registers (Sheet Technical Data 50 Bit POR PIN COP ILOP BCFE IF6 IF5 IF4 IF3 IF14 IF13 IF12 IF11 Unimplemented Memory Map Bit 0 SBSW Note 0 ILAD IF2 IF1 IF10 IF9 IF8 IF7 HVEN MASS ERASE PGM Reserved MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 51
... Register (BRKL) Reset: Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit BPR7 BPR6 BPR5 BPR4 ...
Page 52
... Reserved IF2 $FFF9 Reserved $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) MC68HC908LD60 Memory Map Vector Rev. 1.1 — Freescale Semiconductor ...
Page 53
... RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Random-Access Memory (RAM) Technical Data 53 ...
Page 54
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 54 Random-Access Memory (RAM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 55
... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 4. FLASH Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 FLASH Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13k-Byte FLASH Even Byte Write Buffer (13KEBUF FLASH Block Erase Operation ...
Page 56
... HVEN MASS ERASE PGM BPR3 BPR2 BPR1 HVEN1 MASS1 ERASE1 PGM1 BPR13 BPR12 BPR11 Bit11 Bit10 Bit9 Bit8 47,616 Array 47,616 32 $FFE0–$FFFF $4000–$F9FF (User vectors) 32 bytes by mass 512 bytes erase only MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 57
... Write: Reset: This register controls the 13k-byte array: Address: Read: Write: Reset security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $FE07 Bit Unimplemented Figure 4-2. 47,616-byte FLASH Control Register (FLCR) ...
Page 58
... FLASH even byte write buffer register (13KEBUF) for programming operations. See (13KEBUF) Technical Data 58 4.4.1 13k-Byte FLASH Even Byte Write Buffer and 4.7 FLASH Program Operation. FLASH Memory MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 59
... Use the following procedure to erase a block of FLASH memory: 1. Set the ERASE bit, and clear the MASS bit in the FLASH control 2. Write any data to any FLASH address within the block address 3. Wait for a time, t MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $0066 Bit Bit7 Bit6 ...
Page 60
... Wait for a time Clear the ERASE bit. 7. Wait for a time, t Technical Data 60 (min. 10ms) Erase (min. 5µs) nvh (min. 1µs), the memory can be accessed again in rcv (5µs). nvs (10ms). ERASE (100µs). nvhl MC68HC908LD60 FLASH Memory Rev. 1.1 — Freescale Semiconductor ...
Page 61
... Wait for a time For 47,616-byte array: Write data to the FLASH address Wait for time Repeat step 6 and 7 until all the bytes within the row are MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor (1µs) the memory can be accessed again in read rcv , mode. (Figure 4-5 operation and enables the latching of address and data for programming ...
Page 62
... When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. Technical Data 62 (min. 5µs). nvh (min 1µs), the memory can be accessed in read rcv maximum. See 22.13 FLASH Memory PROG MC68HC908LD60 FLASH Memory Rev. 1.1 — Freescale Semiconductor ...
Page 63
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-5. FLASH Programming Flowchart MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, t ...
Page 64
... These seven bits represent bits [15: 16-bit memory address. Bits [8:0] are logic 0s. Technical Data 64 $FE08 Bit BPR7 BPR6 BPR5 BPR4 $FE0B Bit BPR17 BPR16 BPR15 BPR14 FLASH Memory Bit 0 0 BPR3 BPR2 BPR1 Bit 0 0 BPR13 BPR12 BPR11 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 65
... Examples of block protection for 13k-byte FLASH memory array: and so on... $00–$0B or $40–$FE MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Figure 4-8. FLASH Block Protect Start Address BPR[7:0] $40 The entire 47,616 bytes of FLASH memory is protected. $42 (0100 0010) $4200 (0100 0010 0000 0000) to $FFFF ...
Page 66
... FLASH Memory Technical Data 66 MC68HC908LD60 FLASH Memory Rev. 1.1 — Freescale Semiconductor ...
Page 67
... MCU recommended that this register be written immediately after reset. The configuration register is located at $001F. The configuration register may be read at anytime. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Stop mode recovery time (32 OSCXCLK cycles or 4096 OSCXCLK cycles) ...
Page 68
... Operating Properly 1 = COP module disabled 0 = COP module enabled Technical Data 68 $001F Bit Unimplemented Figure 5-1. Configuration Register (CONFIG) 13 – – 2 (COP).) Configuration Register (CONFIG Bit 0 SSREC COPRS STOP COPD (COP).) 4 OSCXCLK cycles 4 OSCXCLK cycles Section 20. Computer MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 69
... M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Stack Pointer ...
Page 70
... Low-power stop and wait modes 6.4 CPU Registers Figure 6-1 the memory map. Technical Data 70 shows the five CPU registers. CPU registers are not part of Central Processor Unit (CPU) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 71
... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Figure 6-1. CPU Registers Bit Unaffected by reset Figure 6-2. Accumulator (A) Central Processor Unit (CPU) ...
Page 72
... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Technical Data 72 Bit Indeterminate Figure 6-3. Index Register (H:X) Central Processor Unit (CPU) Bit MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 73
... Read: Write: Reset: 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit ...
Page 74
... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Technical Data 74 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 75
... Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result Central Processor Unit (CPU) ...
Page 76
... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock Technical Data 76 Central Processor Unit (CPU) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 77
... Opcode Map See MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock ...
Page 78
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 79
... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...
Page 80
... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 81
... Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – (M (X) – ...
Page 82
... FD 4 IMM DIR EXT IX2 – IX1 SP1 9EE6 ff 4 SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 83
... Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← ...
Page 84
... SP1 9E66 INH IMM DIR EXT IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 85
... TSX Transfer SP to H:X TXA Transfer TXS Transfer H MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Description A ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 86
... Zero bit & Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected Central Processor Unit (CPU) CCR MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 87
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 88
... Central Processor Unit (CPU) Technical Data 88 Central Processor Unit (CPU) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 89
... The MC68HC908LD60 operates from a nominal 24MHz crystal or external clock, providing an 8MHz internal bus clock. The 24MHz clock is required for various modules, such as the CGM. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2) ...
Page 90
... Pierce S To SIM OSCXCLK OSC1 OSC2 can be zero (shorted) when used with S higher-frequency crystals. Refer to manufacturer’s data 24MHz Figure 7-1. Oscillator External Connections Oscillator (OSC) 7-1. This figure shows only To SIM OSCOUT ÷ 2 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 91
... SIM and results in the internal bus frequency being one fourth of the OSCXCLK frequency. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of OSCXCLK to OSC1 and Oscillator (OSC) Oscillator (OSC) ...
Page 92
... SIM module. 7.5.2 Stop Mode The STOP instruction disables the OSCXCLK output. 7.6 Oscillator During Break Mode The oscillator continues drive OSCXCLK when the chip enters the break state. Technical Data 92 MC68HC908LD60 Oscillator (OSC) Rev. 1.1 — Freescale Semiconductor ...
Page 93
... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 CGM I/O Signals External Filter Capacitor Pin (CGMXFC PLL Analog Power Pin (VDDA PLL Analog Ground Pin (VSSA Crystal Output Frequency Signal (OSCXCLK Crystal Reference Frequency Signal (OSCRCLK) ...
Page 94
... Base clock selector circuit; this software-controlled circuit selects either OSCXCLK divided by two or the VCO clock CGMVCLK divided by two, as the base clock DCLK1. The sync processor derives other display clocks from DCLK1. Technical Data 94 Clock Generator Module (CGM) Section 7. Oscillator MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 95
... Section 7. Oscillator OSC2 OSC1 SIMOSCEN (FROM SIM) PHASE-LOCKED LOOP (PLL) HVOCR[1:0] CGMRDV REFERENCE PHASE DETECTOR LOCK DETECTOR LOCK CGMVDV MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor (OSC).) ÷ 2 OSCRCLK DIVIDER BCS V CGMXFC V DDA SSA VRS[7:4] VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG ...
Page 96
... Bit VRS7 VRS6 VRS5 VRS4 HVOCR1 HVOCR0 Reserved Video Modes DCLK DE Video Mode Frequency VGA 640 × 480 24MHz SVGA 800 × 600 40MHz XGA 1024 × 768 64MHz SXGA 1280 × 1024 108MHz MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 97
... VSS pin. NOTE: Route VDDA and VSSA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor (OSC).) should be placed as close to the F F Clock Generator Module (CGM) Clock Generator Module (CGM) CGM I/O Signals Section 7 ...
Page 98
... PLL programming register (PPG) • H & V sync output control register (HVOCR) Technical Data 98 ) and is generated directly from the crystal oscillator XCLK ) and provides the reference for the PLL circuit. XCLK Clock Generator Module (CGM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 99
... PLL control register. Reset clears the PLLF bit. NOTE: The PLLF bit should not be inadvertently cleared. Any read or read- modify-write operation on the PLL control register clears the PLLF bit. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $0038 Bit PLLF PLLIE PLLON ...
Page 100
... Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode • In manual operation, forces the PLL into acquisition or tracking mode Technical Data 100 Clock Generator Module (CGM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 101
... PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $0039 Bit LOCK AUTO ACQ ...
Page 102
... VCO. Address: Read: Write: Reset: Technical Data 102 $003A Bit MUL7 MUL6 MUL5 MUL4 Figure 8-5. PLL Programming Register (PPG) Clock Generator Module (CGM Bit 0 VRS7 VRS6 VRS5 VRS4 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 103
... VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Table 8-2. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 0000 0001 0010 ...
Page 104
... Clock Generator Module (CGM Bit 0 R HVOCR1 HVOCR0 Reserved Video Modes DCLK DE Video Mode Frequency VGA 640 × 480 24MHz SVGA 800 × 600 40MHz XGA 1024 × 768 64MHz SXGA 1280 × 1024 108MHz MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 105
... PLL without turning it off. Applications that require the PLL to wake the MCU from WAIT mode also can deselect the PLL output without turning off the PLL. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Interrupts Technical Data 105 ...
Page 106
... With BCFE at 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Technical Data 106 Section 9. System Integration (SIM). Clock Generator Module (CGM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 107
... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 111 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 111 Reset and System Initialization 112 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Active Resets from Internal Sources ...
Page 108
... SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SIM Break Status Register (SBSR 128 SIM Reset Status Register (SRSR 129 SIM Break Flag Control Register (SBFCR 130 9-1. Figure 9-2 shows a summary of the SIM I/O registers. The System Integration Module (SIM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 109
... RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET RESET PIN CONTROL CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 9-1. SIM Block Diagram ...
Page 110
... OSCXCLK divided by four) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal System Integration Module (SIM Bit 0 SBSW Note 0 ILAD IF2 IF1 IF10 IF9 IF8 IF7 Reserved MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 111
... OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 OSCXCLK cycles. (See Mode.) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor OSCXCLK OSCOUT ÷ 2 OSCILLATOR OSC2 Figure 9-3. OSC Clock Signals ...
Page 112
... SIM (see Table 9-2. PIN Bit Set Table 9-2. PIN Bit Set Timing Number of Cycles Required to Set PIN POR 4163 (4096 + System Integration Module (SIM) (see 9.5 SIM Counter), but an Registers). Timing). Figure 9 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 113
... The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. OSCXCLK MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor RST IAB PC Figure 9-4. External Reset Timing Timing). An internal reset can be caused by an illegal Reset). Note that for POR resets, the SIM cycles through Figure 9-5 ...
Page 114
... The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. OSC1 PORRST OSCXCLK OSCOUT RST IAB Technical Data 114 4096 32 32 CYCLES CYCLES CYCLES Figure 9-7. POR Recovery System Integration Module (SIM) $FFFE $FFFF MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 115
... The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 4 – 2 OSCXCLK cycles, drives the COP counter. The COP should be System Integration Module (SIM) System Integration Module (SIM) ...
Page 116
... OSCXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. Technical Data 116 System Integration Module (SIM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 117
... Normally, sequential program execution can be changed in three different ways: • • • MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor for counter control and internal reset Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts System Integration Module (SIM) ...
Page 118
... SP – 4 VECT CCR . Figure 9-8 Interrupt Entry SP – – – 1[7:0] PC – 1[15:8] Figure 9-9. Interrupt Recovery System Integration Module (SIM) flow charts the handling of Figure VECT L START ADDR V DATA H V DATA L OPCODE OPCODE OPERAND MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 119
... YES (As many interrupts as exist on chip) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO YES DDC12AB INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. YES SWI INSTRUCTION? NO YES RTI INSTRUCTION? NO Figure 9-10. Interrupt Processing ...
Page 120
... Technical Data 120 Processing.) CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 9-11 Interrupt Recognition Example System Integration Module (SIM) Figure Figure 9-11 BACKGROUND ROUTINE MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 121
... The interrupt status registers can be useful for debugging. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Table 9-3 summarizes the interrupt sources and the interrupt System Integration Module (SIM) System Integration Module (SIM) Exception Control Technical Data ...
Page 122
... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 123
... Bit 1and Bit 0 — Always read 0 9.6.2.2 Interrupt Status Register 2 Address: Read: Write: Reset: IF14–IF7 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $FE04 Bit IF6 IF5 IF4 ...
Page 124
... Upon leaving break mode, execution of the second step will clear the flag as normal. Technical Data 124 (BRK)). The SIM puts the CPU into the System Integration Module (SIM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 125
... Figure 9-15 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Figure 9-14 shows the timing for wait mode entry. IAB WAIT ADDR WAIT ADDR + 1 IDB ...
Page 126
... IDB $A6 $A6 $A6 $01 Figure 9-15. Wait Recovery from Interrupt or Break 32 Cycles $6E0B $A6 $A6 $A6 Figure 9-16. Wait Recovery from Internal Reset System Integration Module (SIM) $00FF $00FE $00FD $00FC $0B $6E 32 Cycles RST VCT H RST VCT L MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 127
... NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. OSCXCLK INT/BREAK IAB Figure 9-18. Stop Mode Recovery from Interrupt or Break MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Figure 9-17 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W Figure 9-17 ...
Page 128
... Table 9-4. SIM Registers Summary Address Register $FE00 SBSR $FE01 SRSR $FE03 SBFCR $FE00 Bit Reserved Figure 9-19. SIM Break Status Register (SBSR) System Integration Module (SIM) Table 9-4 shows the Access Mode User User User Bit 0 SBSW Note 0 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 129
... Read: Write: POR: POR — Power-On Reset Bit PIN — External Reset Bit MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ...
Page 130
... MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Technical Data 130 $FE03 Bit BCFE Reserved System Integration Module (SIM Bit MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 131
... V vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Data Format ...
Page 132
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 132 1 Figure 10-1 shows a sample circuit used to enter monitor Monitor ROM (MON reset vector is TST , is applied to TST MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 133
... SW2: Position D — For monitor mode entry when reset vector is blank ($FFFE and $FFFF = $FF): Bus clock = OSCXCLK ÷ 4; PTC0, PTC1, and PTC3 voltages are not required. 3. See Table 22-4 for IRQ voltage level requirements. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor V TST 10 Ω SW2 C (See NOTES) D ...
Page 134
... The break signal also provides a timing reference to allow the host to determine the necessary baud rate. Technical Data 134 shows the pin conditions for entering monitor mode. As 9.8304 MHz with PTC3 high Monitor ROM (MON) ) TST Table 10-1 after MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 135
Table 10-1. Monitor Mode Signal Requirements and Options Address IRQ RST $FFFE/ PTC3 PTC1 $FFFF X GND TST TST TST TST ...
Page 136
... Disabled ) is removed from the IRQ pin, the SIM asserts its COP enable TST Figure 10-2 Monitor ROM (MON) is applied TST SWI SWI Vector Vector High Low $FFFC $FFFD $FEFC $FEFD and Figure 10-3.) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 137
... A start bit followed by nine low bits is a break signal (see Figure 10-5). When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor BIT 0 BIT 1 BIT 2 BIT 3 BIT Figure 10-2 ...
Page 138
... Read byte from memory Specifies 2-byte address in high byte:low byte order Data Returns contents of specified address $4A Command Sequence ADDRESS ADDRESS ADDRESS READ HIGH HIGH LOW Monitor ROM (MON) TWO-STOP-BIT DELAY BEFORE ZERO ECHO ADDRESS DATA LOW RETURN MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 139
... Description Operand Returned ECHO Description Operand Returned MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Table 10-4. WRITE (Write Memory) Command Write byte to memory Specifics 2-byte address in high byte:low byte order; low byte followed by data byte Data None Opcode $49 Command Sequence SEMT TO MONITOR ...
Page 140
... IWRITE ECHO Table 10-7. READSP (Read Stack Pointer) Command Reads stack pointer None Returns stack pointer in high byte:low byte order $0C Command Sequence SENT TO MONITOR READSP READSP ECHO Monitor ROM (MON) DATA SP SP HIGH LOW RETURN MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 141
... PTC3 pin upon entry into monitor mode. When PTC3 is high, the divide by ratio is 1024. If the PTC3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Table 10-8. RUN (Run User Program) Command Executes RTI instruction None Data None ...
Page 142
... Monitor ROM (MON) Technical Data 142 Monitor ROM (MON) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 143
... TIM Counter Modulo Registers (TMODH:TMODL 158 11.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 159 11.10.5 TIM Channel Registers (TCH0H/L:TCH1H/ 162 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 11. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 TIM Counter Prescaler ...
Page 144
... The TIM shares the TCH0 pin with the sync processor CLAMP output. Technical Data 144 is a block diagram of the TIM. Table 11-1. Pin Name Conventions TIM Generic Pin Name: Full TIM Pin Name: Pin Selected for TCH0 By: Timer Interface Module (TIM) TCH0 CLAMP/TCH0 ELS0B:ELS0A MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 145
... COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor shows the structure of the TIM. The central component of PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A ...
Page 146
... PS2 PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 147
... When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit Bit15 Bit14 ...
Page 148
... Technical Data 148 11.5.3 Output Compare. The pulses are Timer Interface Module (TIM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 149
... Program the TIM to set the pin if the state of the PWM pulse is logic zero. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Figure 11-2 shows, the output compare value in the TIM channel Timer Interface Module (TIM) Timer Interface Module (TIM) Functional Description ...
Page 150
... WIDTH OUTPUT COMPARE Figure 11-2. PWM Period and Pulse Width (see 11.10.1 TIM Status and Control Register 11.5.4 Pulse Width Modulation Timer Interface Module (TIM) OVERFLOW OUTPUT OUTPUT COMPARE COMPARE (TSC)). (PWM). The pulses are MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 151
... I/O pin. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value ...
Page 152
... PWM signals) to the mode select bits, MSxB:MSxA. (See Table 11-3.) compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Timer Interface Module (TIM) Table 11-3.) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 153
... CPU interrupt request from the TIM can bring the MCU out of wait mode. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor TIM overflow flag (TOF) — The TOF bit is set when the TIM counter value rolls over to $0000 after matching the value in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests ...
Page 154
... CLAMP output signal. TCH0 pin is programmable independently as an input capture pin or an output compare pin. It also can be configured as a buffered output compare or buffered PWM pin. Technical Data 154 21.6.4 SIM Break Flag Control Timer Interface Module (TIM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 155
... TOF is set and then writing a logic zero to TOF. If another TIM MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) ...
Page 156
... PS[2:0] — Prescaler Select Bits These read/write bits select either the TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as shows. Reset clears the PS[2:0] bits. Technical Data 156 Timer Interface Module (TIM) Table 11-2 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 157
... TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. Address: Read: Write: Reset: Address: Read: Write: Reset: MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Table 11-2. Prescaler Selection PS1 PS0 ...
Page 158
... Reset the TIM counter before writing to the TIM counter modulo registers. Technical Data 158 $000E TMODH Bit Bit15 Bit14 Bit13 Bit12 $000F TMODL Bit Bit7 Bit6 Bit5 Bit4 Timer Interface Module (TIM Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 159
... When channel x is MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare ...
Page 160
... When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. (See 1 = Initial output level low 0 = Initial output level high Technical Data 160 Table 11-3. Table 11-3.) Reset clears the MSxA bit. Timer Interface Module (TIM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 161
... Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor shows how ELSxB and ELSxA work. Reset clears the Table 11-3. Mode, Edge, and Level Selection MSxA ELSxB ...
Page 162
... Technical Data 162 shows, the CHxMAX bit takes effect in the cycle after it OVERFLOW OVERFLOW OVERFLOW PERIOD OUTPUT OUTPUT COMPARE COMPARE Figure 11-7. CHxMAX Latency Timer Interface Module (TIM) OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 163
... Address: Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $0011 TCH0H Bit Bit15 Bit14 Bit13 Indeterminate after reset $0012 TCH0L Bit Bit7 Bit6 Bit5 Indeterminate after reset $0014 ...
Page 164
... Timer Interface Module (TIM) Technical Data 164 Timer Interface Module (TIM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 165
... The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Example of the waveforms are shown in MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 PWM Registers 167 PWM Data Registers (0PWM–7PWM 167 PWM Control Register (PWMCR 168 ...
Page 166
... PWM3E PWM2E PWM1E PWM0E MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 167
... The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Examples of PWM output waveforms are shown in Figure MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor PWM data registers ($0070–$0077) PWM control register ($0078) $0070–$0077 Bit ...
Page 168
... PTB0 PWM0 PTB1 PWM1 PTB2 PWM2 PTB3 PWM3 PTB4 PWM4 PTB5 PWM5 PTB6 PWM6 PTB7 PWM7 Pulse Width Modulator (PWM Bit 0 PWM3E PWM2E PWM1E PWM0E Control Bit PWM0E PWM1E PWM2E PWM3E PWM4E PWM5E PWM6E PWM7E MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 169
... N = value set in 3-bit BRM (bit0-bit2) N xx1 x1x 1xx Figure 12-4. 8-Bit PWM Output Waveforms MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 1 PWM cycle = 32T 31T 16T 31T Pulse inserted at end of PWM cycle depends on setting of N. PWM cycles where pulses are Number of inserted pulses in ...
Page 170
... Pulse Width Modulator (PWM) Technical Data 170 Pulse Width Modulator (PWM) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 171
... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Interrupts .175 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Wait Mode ...
Page 172
... Figure 13-1. ADC I/O Register Summary Technical Data 172 Bit AIEN ADCO ADCH4 AD7 AD6 AD5 AD4 Unaffected after Reset 0 ADIV2 ADIV1 ADIV0 Unimplemented Analog-to-Digital Converter (ADC Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 173
... READ DDRC WRITE DDRC WRITE PTC READ PTC CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO BUS CLOCK MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Figure 13-2 DDRCx RESET PTCx ADC DATA REGISTER ADC VOLTAGE IN ADCVIN ADC ADC CLOCK CLOCK GENERATOR ADIV[2:0] ADICLK Figure 13-2. ADC Block Diagram ...
Page 174
... With a 1MHz ADC internal clock the maximum sample rate is 62.5kHz. Technical Data 174 16 to17 ADC cycles Conversion time = Number of bus cycles = conversion time × bus frequency Analog-to-Digital Converter (ADC) ADC frequency MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 175
... If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to logic 1’s before executing the WAIT instruction. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Table 2-1 . Vector Addresses. Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) Interrupts ...
Page 176
... ADC Voltage Reference Low Pin (VRL) VRL is the low voltage reference for the ADC. 13.7.5 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the six ADC channels to the ADC module. Technical Data 176 Analog-to-Digital Converter (ADC) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 177
... The interrupt signal is cleared when the data register is read or the status and control register is written. Reset clears the AIEN bit. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ADC status and control register (ADSCR) ADC data register (ADR) ADC input clock register (ADICLK) $003B Bit 7 ...
Page 178
... ADC1 1 0 ADC2 1 1 ADC3 0 0 ADC4 0 1 ADC5 1 0 ↓ ↓ Analog-to-Digital Converter (ADC) Input Select PTC0/ADC0 PTC1/ADC1 PTC2/ADC2 PTC3/ADC3 PTC4/ADC4 PTC5/ADC5 (1) — Unused — Reserved — Unused VRH VRL ADC power off MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 179
... ADIV[2:0] — ADC Clock Prescaler Bits ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. available clock configurations. The ADC clock should be set to approximately 1MHz. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $003C Bit AD7 AD6 ...
Page 180
... Table 13-2. ADC Clock Divide Ratio ADIV1 ADIV0 Analog-to-Digital Converter (ADC) ADC Clock Rate ADC Input Clock ÷ 1 ADC Input Clock ÷ 2 ADC Input Clock ÷ 4 ADC Input Clock ÷ 8 ADC Input Clock ÷ 16 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 181
... It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Multi-Master IIC Address Register (MMADR 184 Multi-Master IIC Control Register (MMCR) ...
Page 182
... Generic Pin Names: SDA SCL Technical Data 182 Full MCU Pin Names: PTD7/IICSDA IICDATE bit in PDCR ($0069) PTD6/IICSCL IICSCLE bit in PDCR ($0069) Multi-Master IIC Interface (MMIIC) . The maximum DD Table 14-1. The generic Pin Selected for IIC Function By: MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 183
... Data Receive Register Write: $006F (MMDRR) Reset: Figure 14-1. MMIIC I/O Register Summary 14.5 Multi-Master IIC Registers Six registers are associated with the Multi-master IIC module, they are outlined in the following sections. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit MMBB MMAST MMAD7 ...
Page 184
... MMIIC responds to address $00 and $MMAD[7: MMIIC responds to address $MMAD[7:1] Technical Data 184 $006B Bit MMAD7 MMAD6 MMAD5 MMAD4 MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD Bit Multi-Master IIC Interface (MMIIC Bit 0 MMAD3 MMAD2 MMAD1 MMEXTAD Bit MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 185
... This bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. When MMTXAK is cleared, an acknowledge signal will be sent at the 9th clock bit. Reset clears this bit. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor $006C Bit MMEN ...
Page 186
... MMIIC is disabled. Reset clears this bit Start condition detected 0 = Stop condition detected or MMIIC is disabled Technical Data 186 $006A Bit MMBB MMAST Multi-Master IIC Interface (MMIIC Bit 0 MMRW MMBR2 MMBR1 MMBR0 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 187
... WAIT instruction places the MCU in wait mode, with CPU clock is halted. These bits are cleared upon reset. (See Baud Rate MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 1 = Master mode operation 0 = Slave mode operation 1 = Master mode receive 0 = Master mode transmit Select.) ...
Page 188
... MMBR1 MMBR0 NOTE: CPU bus clock is external clock ÷ 6MHz $006D Bit MMTXIF MMATCH MMSRW MMRXAK Unimplemented Multi-Master IIC Interface (MMIIC) Baud Rate 750k 375k 187.5k 93.75k 46.875k 23.437k 11.719k 5.859k Bit 0 0 MMTXBE MMRXBF MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 189
... SDA line for the master to generate "stop" or "repeated start" condition. Reset sets this bit. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 1 = Data transfer completed 0 = Data transfer in progress 1 = Received address matches MMADR 0 = Received address does not match 1 = Slave mode transmit ...
Page 190
... Technical Data 190 $006E Bit MMTD7 MMTD6 MMTD5 MMTD4 Multi-Master IIC Interface (MMIIC Bit 0 MMTD3 MMTD2 MMTD1 MMTD0 MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 191
... MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor the module receives an acknowledge bit (MMRXAK = 0), after setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0) ...
Page 192
... MMBB flag. This is the only way to clear the MMBB flag by software if the module hangs up due STOP condition received. The MMIIC can resume operation again by setting the MMEN bit. Technical Data 192 Figure 14-8. Multi-Master IIC Interface (MMIIC) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 193
... Slave Receive Mode START Address MMTXBE=0 MMRXBF=0 KEY: shaded data packets indicate a transmit by the MCU’s MMIIC module Figure 14-8. Data Transfer Sequences for Master/Slave Transmit/Receive Modes MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor 0 ACK TX Data1 ACK MMTXBE=1 MMTXBE=1 MMTXIF=1 MMTXIF=1 Data2 → MMDTR Data3 → ...
Page 194
... Multi-Master IIC Interface (MMIIC) Technical Data 194 Multi-Master IIC Interface (MMIIC) MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 195
... It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Section 15. DDC12AB Interface Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DDC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 DDC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 DDC Address Register (DADR) ...
Page 196
... Table 15-1. Pin Name Conventions DDC12AB Generic Pin Names: SDA SCL Technical Data 196 Full MCU Pin Names: PTD5/DDCSDA DDCDATE bit in PDCR ($0069) PTD4/DDCSCL DDCSCLE bit in PDCR ($0069) DDC12AB Interface . The DD Table 15-1. Pin Selected for DDC Function By: MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 197
... Data Transmit Register Write: (DDTR) Reset: Read: DDC Data Receive Register $001B Write: (DDRR) Reset: Read: DDC2 Address Register $001C Write: (D2ADR) Reset: Figure 15-1. DDC I/O Register Summary MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor Bit ALIF NAKIF BB MAST DAD7 DAD6 DAD5 DAD4 1 0 ...
Page 198
... Reset sets a default value of $A0. Technical Data 198 $0017 Bit DAD7 DAD6 DAD5 DAD4 Figure 15-2. DDC Address Register (DADR) DDC12AB Interface Bit 0 DAD3 DAD2 DAD1 EXTAD MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...
Page 199
... These seven bits represent the second slave address for the DDC2BI protocol. D2AD[7:1] should be set to the same value as DAD[7:1] in DADR if user application do not use DDC2BI. Reset clears all bits this register. MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor DAD7 DAD6 DAD5 Bit 7 ...
Page 200
... DDC does not send acknowledge signals at 9th clock bit 0 = DDC sends acknowledge signal at 9th clock bit Technical Data 200 $0018 Bit DEN DIEN Unimplemented Figure 15-4. DDC Control Register (DCR) request to CPU interrupt request to CPU DDC12AB Interface Bit 0 0 TXAK SCLIEN DDC1EN MC68HC908LD60 Rev. 1.1 — Freescale Semiconductor ...