E28F320J3A110 Intel, E28F320J3A110 Datasheet - Page 37

• Manufacturer Part Number: E28F320J3A110
• Manufacturer: Intel

Specifications of E28F320J3A110

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

10.0
10.1
10.1.1
Datasheet
Read Operations
The device supports four types of read modes: Read Array, Read Identifier, Read Status, and CFI
query. Upon power-up or return from reset, the device defaults to read array mode. To change the
device’s read mode, the appropriate read-mode command must be written to the device. (See
Section 9.2, “Device Commands” on page
details regarding read status, read ID, and CFI query modes.
Upon initial device power-up or after exit from reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read
Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control signals dictate the
data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be
enabled (see
obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled
(see
active, drives the selected memory data onto the I/O bus. WE# must be at V
Read Array
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to
read array mode. The device defaults to four-word asynchronous read page mode. The Read Array
command also causes the device to enter read array mode. The device remains enabled for reads
until another command is written. If the internal WSM has started a block erase, program, or lock-
bit configuration, the device will not recognize the Read Array command until the WSM completes
its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read
Array command functions independently of the V
Asynchronous Page Mode Read
There are two Asynchronous Page mode configurations that are available depending on the user’s
system design requirements:
After the initial access delay, the first word out of the page buffer corresponds to the initial address.
In Four-Word Page mode, address bits A[2:1] determine which word is output from the page buffer
for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus
width. Subsequent reads from the device come from the page buffer. These reads are output on
D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0]
(Four-Word Page mode) or A[3:0] (Eight-Word Page mode) are the only address bits that change.
Data can be read from the page buffer multiple times, and in any order. In Four-Word Page Mode,
if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is
toggled, the device will sense and load new data into the page buffer. Asynchronous Page Mode is
the default read mode on power-up or reset.
•
•
Four-Word Page mode: This is the default mode on power-up or reset. Array data can be
sensed up to four words (8 Bytes) at a time.
Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a time. This
mode must be enabled on power-up or reset by using the command sequence found in
Table 14, “Command Bus-Cycle Definitions” on page
which word is output during a read operation, and A[3:0] determine which byte is output for a
x8 bus width.
Table
13), select the memory device. OE# is the data output (D[15:0]) control and, when
Table 13, “Chip Enable Truth Table” on page
35.) See
PEN
Section 14.0, “Special Modes” on page 50
voltage.
33), and OE# must be driven active to
35. Address bits A[3:1] determine
256-Mbit J3 (x8/x16)
IH
.
for
37