TB28F008S3-150 Intel, TB28F008S3-150 Datasheet
TB28F008S3-150
Specifications of TB28F008S3-150
Related parts for TB28F008S3-150
TB28F008S3-150 Summary of contents
Page 1
... GND, selective hardware block locking, or flexible software block locking. These PP alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged 44-lead PSOP. Based on the 28F008SA architecture, the 3 Volt FlashFile memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. NOTE: This document formerly known as Byte-Wide Smart 3 FlashFile™ ...
Page 2
... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
Page 3
INTRODUCTION............................................. 5 1.1 New Features .............................................. 5 1.2 Product Overview ........................................ 5 1.3 Pinout and Pin Description........................... 6 2.0 PRINCIPLES OF OPERATION..................... 11 2.1 Data Protection.......................................... 12 3.0 BUS OPERATION ........................................ 12 3.1 Read.......................................................... 12 3.2 Output Disable........................................... 12 ...
Page 4
... Added BGA* CSP pinouts and corrected error in PSOP pinout Added Design Consideration for V devices -005 Added maximum Block Erase time for 2.7 V operation Name of document changed from Byte-Wide Smart 3 FlashFile™ Memory Family 4, 8, and 16 Mbit 4 Description Test Conditions, previously read V ...
Page 5
... Section 8.0. 1.1 New Features The 3 Volt FlashFile memory family maintains backwards-compatibility with Intel ® 28F008SA-L. Key enhancements include: SmartVoltage Technology Enhanced Suspend Capabilities In-System Block Locking They share a compatible status register, software commands, and pinouts ...
Page 6
To protect programmed data, each block can be locked. This block locking mechanism uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock individual blocks. The block lock-bits gate block erase and program operations, ...
Page 7
... SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device CC for optimized read performance. Do not float any power pins. 3 Volt Flash With all write attempts to the flash memory are inhibited. Device CC LKO operations at invalid V results and should not be attempted. Block erase, program, and lock-bit configuration operations with V GND SUPPLY GROUND: Do not float any ground pins ...
Page 8
...
Page 9
Figure 3. PSOP 44-Lead Pinout PRELIMINARY 28F004S3/28F008S3/28F016S3 9 ...
Page 10
... This is the view of the package as surface mounted on the board. Note that the signals are mirror images of bottom view. NOTES: 1. Figures are not drawn to scale. 2. Address A is not included in the 28F008S3 More information on µBGA* packages is available by contacting your Intel/Distribution sales office. Figure 4. µBGA* CSP 40-Bump Pinout (28F008S3 and 28F016S3 RP# V ...
Page 11
... Read Array command. Block erase suspend allows system software to suspend a block erase to read data from or program data to any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location. PRELIMINARY 28F004S3/28F008S3/28F016S3 1FFFFF ...
Page 12
... CPU initialization may not occur because the flash IH memory may be providing status information instead of array data. Intel’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
Page 13
Block 31 Reserved for Future Implementation 1F0002 Block 31 Lock Configuration Reserved for Future Implementation 1F0000 (Blocks 16 through 30) 0FFFFF Block 15 Reserved for Future Implementation Block 15 Lock Configuration 0F0002 Reserved for Future Implementation 0F0000 (Blocks 8 ...
Page 14
Mode Notes RP# Read 1,2 Output Disable Standby Deep Power-Down Read Identifier Codes Write ...
Page 15
... If the master lock-bit is set, RP# must clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP Commands other than those shown above are reserved by Intel for future device implementations and should not be used. PRELIMINARY 28F004S3/28F008S3/28F016S3 ...
Page 16
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads ...
Page 17
... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
Page 18
... The only other valid commands while program is suspended are Read Status Register and Program Resume. After Program Resume command is written to the flash memory, the WSM will continue the program process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V ...
Page 19
Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master ...
Page 20
Table 6. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed ...
Page 21
Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block Erase Loop No 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
Page 22
Start Write 40H, Address Write Byte Data and Address Read Status Register Suspend Program Loop No 0 Suspend SR.7 = Program 1 Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...
Page 23
Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program ? Program Read Array No Loop Data Done? Yes Write D0H Write FFH Block Erase Resumed Read Array ...
Page 24
Start Write B0H Read Status Register 0 SR Program Completed SR Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Program Resumed Read Array Data Figure 10. Program Suspend/Resume Flowchart ...
Page 25
Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
Page 26
Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error PP 0 ...
Page 27
... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections: CE#, OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation. b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
Page 28
... V Program and Erase PP Voltages on Sub-0.4µ S3 Memory Family The Intel 3 Volt FlashFile™ memory family provides in-system program/erase at 2.7 V and 3 well as faster factory program/erase Future sub-0.4 µ lithography 3 Volt FlashFile memory products will also include a backward- compatible 12 V programming feature. This mode, however, is not intended for extended use ...
Page 29
... PRELIMINARY 28F004S3/28F008S3/28F016S3 NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" ...
Page 30
DC Characteristics—Commercial Temperature Sym Parameter Notes Typ I Input Load Current Output Leakage Current Standby Current 1,3,6 CCS Deep Power-Down 1 CCD CC Current I V Read Current ...
Page 31
DC Characteristics— Commercial Temperature Sym Parameter Notes Min V Input Low Voltage Input High Voltage Output Low Voltage 3,7 OL 3,7 V Output High Voltage OH1 (TTL) 3,7 V Output High Voltage OH2 ...
Page 32
INPUT 1.35 0.0 AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% ...
Page 33
V IH RY/BY# ( RP# ( Figure 16. AC Waveform for Reset Operation Table 7. Reset Specifications # Sym Parameter P1 t RP# Pulse Low Time (If RP# is tied to V PLPH ...
Page 34
AC Characteristics—Read-Only Operations °C to +70 °C A 3.3V ± 0.3V V Versions (4) 2.7V 3. Sym Parameter R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t ...
Page 35
Standby Address Selection V IH ADDRESSES ( CE# ( OE# ( WE# ( DATA (D/Q) High Z (DQ0-DQ7 ...
Page 36
AC Characteristics—Write Operations °C to +70 °C A Versions (4) # Sym RP# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# ...
Page 37
ADDRESSES [ CE# (WE#) [E(W OE# [ WE# (CE#) [W(E High Z DATA ...
Page 38
Block Erase, Program, and Lock-Bit Configuration Performance Commercial Temperature V = 3.3V ± 0.3V °C to +70 ° Sym Parameter W16 t Byte Program Time WHRH1 t EHRH1 Block Program Time W16 ...
Page 39
... Current NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications. 6.10 AC Characteristics—Read-Only Operations T = –40 °C to +85 °C ...
Page 40
... E28F004S3-150 E28F008S3-150 PA28F004S3-120 PA28F008S3-120 PA28F004S3-150 PA28F008S3-150 G28F008S3-120 G28F008S3-150 TE28F004S3-150 TE28F008S3-150 TB28F004S3-150 TB28F008S3-150 NOTE: 1. Contact your local Intel or distribution sales office to order components with 2 Access Speed (ns) 120 ns (3.3 V), 150 ns (2.7 V) Voltage Options ( Smart 3 Flash (2.7 V/ 2.7 V and 3.3 V/3.3 V and 12 V) Product Family S = FlashFile™ ...
Page 41
... Models Sales Office NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...