MT48LC16M8A2TG-75 Micron Technology Inc, MT48LC16M8A2TG-75 Datasheet

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MT48LC16M8A2TG-75

Manufacturer Part Number
MT48LC16M8A2TG-75
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC16M8A2TG-75

Organization
16Mx8
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant

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SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site:
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge, and
• Self refresh mode; standard and low power
• 64ms, 4,096-cycle refresh (commercial & industrial)
• 16ms, 4,096-cycle refresh (Automotive)
• LVTTL-compatible inputs and outputs
• Single +3.3 ±0.3V power supply
Notes:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_1.fm - Rev. N 1/09 EN
Options
• Configurations
• Write recovery (
• Package/Pinout
• Timing (cycle time)
• Self refresh
• Design revision
• Operating temperature range
of system clock
changed every clock cycle
auto refresh modes
– 32 Meg x 4 (8 Meg x 4 x 4 banks)
– 16 Meg x 8 (4 Meg x 8 x 4 banks)
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
– Plastic package – OCPL
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
– 60-ball FBGA (8mm x 16mm)
– 60-ball FBGA (8mm x 16mm) Pb-free
– 54-ball VFBGA (8mm x 8mm)
– 54-ball VFBGA (8mm x 8mm) Pb-free
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– 6.0ns @ CL = 3 (x16 only)
– Standard
– Low power
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
t
WR = “2 CLK”
1. Refer to Micron technical note: TN-48-05.
2. Off-center parting line.
3. Consult Micron for availability.
4. x16 only.
Products and specifications discussed herein are subject to change by Micron without notice.
t
WR)
1
2
Designator
32M4
16M8
8M16
None
None
BB
FB
B4
-6A
AT
F4
-75
-7E
TG
IT
A2
:G
P
L
3
4
4
3
3
3
www.micron.com
1
Figure 1:
Notes:
Table 1:
Table 2:
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Speed
Grade
-6A
-7E
-7E
-75
-75
DQ0
DQ1
x4
NC
NC
NC
NC
NC
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1. The # symbol indicates signal is active LOW. A dash (-) indicates
DQ0
DQ1
DQ2
DQ3
x8
NC
NC
NC
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x8 and x4 pin function is same as x16 pin function.
Frequency
DQML
x16
V
V
CAS#
RAS#
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
VssQ
VssQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WE#
BA0
BA1
DD
DD
A10
V
V
CS#
V
Clock
A0
A1
A2
A3
DD
DD
DD
Q
Q
Address Table
Key Timing Parameters
CL = CAS (Read) latency
54-Pin TSOP Pin Assignment
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8 Meg x 4 x 4
4 (BA0, BA1)
32 Meg x 4
4K (A0–A11)
2K (A0–A9,
128Mb: x4, x8, x16 SDRAM
banks
A11)
4K
CL = 2
5.4ns
6ns
Access Time
©1999 Micron Technology, Inc. All rights reserved.
CL = 3
4 Meg x 8 x 4
4K (A0–A11)
4 (BA0, BA1)
5.4ns
5.4ns
5.4ns
16 Meg x 8
1K (A0–A9)
banks
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
4K
Setup
Time
x16
Vss
DQ15
VssQ
DQ14
DQ13
V
DQ12
DQ11
VssQ
DQ10
DQ9
V
DQ8
Vss
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
DD
DD
Q
Q
2 Meg x 16 x 4
Features
4K (A0–A11)
4 (BA0, BA1)
8 Meg x 16
512 (A0–A8)
x8
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
banks
4K
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
Hold
Time
0.8ns
0.8ns
0.8ns
0.8ns
0.8ns
x4
-

Related parts for MT48LC16M8A2TG-75

MT48LC16M8A2TG-75 Summary of contents

Page 1

... Automotive (–40°C to +105°C) Notes: 1. Refer to Micron technical note: TN-48-05. 2. Off-center parting line. 3. Consult Micron for availability. 4. x16 only. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_1.fm - Rev. N 1/09 EN Products and specifications discussed herein are subject to change by Micron without notice. www.micron.com Figure x16 ...

Page 2

... Table 3: 128Mb SDRAM Part Numbers Part Number MT48LC32M4A2TG MT48LC32M4A2P MT48LC16M8A2TG MT48LC16M8A2P MT48LC16M8A2FB MT48LC16M8A2BB MT48LC8M16A2TG MT48LC8M16A2P MT48LC8M16A2B4 MT48LC8M16A2F4 Notes: 1. FBGA Device Decode: http://www.micron.com/support/FBGA/FBGA.asp General Description The Micron containing 134,217,728 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...

Page 3

... Self refresh not supported • Ambient and case temperature cannot be less than –40°C or greater than +105°C PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_1.fm - Rev. N 1/09 EN 128Mb: x4, x8, x16 SDRAM Automotive Temperature Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 4

... Electrical Specifications .46 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Timing Diagrams .53 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAMTOC.fm - Rev. N 1/09 EN 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©1999 Micron Technology, Inc. All rights reserved. Table of Contents ...

Page 5

... Figure 53: Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Figure 54: WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Figure 55: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Figure 56: 54-Pin Plastic TSOP (400 mil .72 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAMLOF.fm - Rev RCD (MIN) When 2 < RCD (MIN)/ 5 128Mb: x4, x8, x16 SDRAM List of Figures t CK ≤ .25 Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...

Page 6

... FBGA “FB/BB” Package (x8 device), 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Figure 58: 54-Ball VFBGA “F4/B4” Package (x16 device), 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAMLOF.fm - Rev. N 1/09 EN 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 6 ©1999 Micron Technology, Inc. All rights reserved. ...

Page 7

... List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 3: 128Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 4: Pin/Ball Descriptions .13 Table 5: Burst Definition .19 Table 6: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 7: Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 8: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 9: Truth Table 3 – Current State Bank n, Command to Bank .42 Table 10: Truth Table 4 – ...

Page 8

... FBGA Ball Assignments Figure 2: 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev DQ7 Vss VssQ DQ6 DD NC DQ5 NC VssQ DQ4 Vss DQM CKE NC A11 Vss Depopulated Balls Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 9

... VFBGA Assignments (Top View), 8 Meg x 16, 8mm x 8mm Notes: 1. The balls at A4, A5, and A6 are not in the physical package. They are included in the draw- ing to illustrate that rows 4, 5, and 6 exist but contain no solder balls. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev DQ15 DQ14 DQ13 ...

Page 10

... CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 11 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev BANK0 ROW- 12 ROW- ADDRESS ADDRESS MUX MEMORY 4,096 LATCH & (4,096 x 2,048 x 4) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC ...

Page 11

... CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 10 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev BANK0 ROW- 12 ROW- ADDRESS ADDRESS MUX MEMORY 4,096 LATCH & (4,096 x 1,024 x 8) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC ...

Page 12

... CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 9 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev BANK0 ROW- 12 ADDRESS ROW- ADDRESS MUX MEMORY 4,096 LATCH & (4,096 x 512 x 16) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC ...

Page 13

... PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. L2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...

Page 14

... D7 1, 14, 27 A9, E7, J9 A7, R7 28, 41, 54 A1, E3, J1 A2, H2, R2 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Symbol Type Description – DQ0– x16: I/O Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42, DQ15 45, 48, and 51 are NCs for x8; and 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4). DQ0– ...

Page 15

... Functional Description In general, the 128Mb SDRAMs (8 Meg banks, 4 Meg banks, and 2 Meg banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous inter- face (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns by 4 bits. Each of the x8’ ...

Page 16

... Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode, and a write burst mode, as shown in Figure 7 on page 18. The mode register is programmed via the LMR command and will retain the stored information until it is programmed again or the device loses power ...

Page 17

... The ordering of accesses within a burst is determined by the BL, the burst type, and the starting column address, as shown in Table 5 on page 19. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 128Mb: x4, x8, x16 SDRAM Functional Description Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 18

... Write Burst Mode A9 0 Programmed Burst Length 1 Single Location Access A8 A7 A6–A0 Operating Mode 0 0 Defined Standard Operation – – – All other states reserved PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN A11 A10 Reserved WB Op Mode CAS Latency Program CAS Latency ...

Page 19

... T2, as shown in Figure 8 on page 20. Table 6 on page 20 indicates the operating frequen- cies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Order of Accesses Within a Burst Starting Column Address Type = Sequential ...

Page 20

... Write Burst Mode When the BL programmed via M0–M2 applies both to read and write bursts; when the programmed BL applies to read bursts, but write accesses are single- location (nonburst) accesses. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Speed -6A -7E -75 T0 ...

Page 21

... SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM, which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...

Page 22

... Auto precharge is a feature that performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev MRD is met. t RP) after the PRECHARGE command is issued. Input A10 determines Micron Technology, Inc ...

Page 23

... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become “ ...

Page 24

... The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of 2 clocks) for time is required for the completion of any internal refresh in progress ...

Page 25

... CL setting. Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN CLK CKE HIGH CS# ...

Page 26

... Figure 11: READ Command A0–A9, A11: x4 A0–A9: x8 A0–A8: x16 A9, A11: x16 Figure 12: CAS Latency COMMAND COMMAND PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN CLK CKE HIGH CS# RAS# CAS# WE# COLUMN ADDRESS A11: x8 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BANK BA0, BA1 ...

Page 27

... This is shown in Figure 13 for and data element either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a prefetch archi- tecture. A READ command can be initiated on any clock cycle following a previous READ command ...

Page 28

... READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...

Page 29

... PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev ...

Page 30

... This is shown in Figure 18 on page 31 for each possible CL; data element the last desired data element of a longer burst. Figure 17: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS Notes: 1. DQM is LOW. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev met. Note that part of the row precharge time CLK READ NOP NOP BANK a, ...

Page 31

... DQ will remain High-Z and any additional input data will be ignored (see Figure 20 on page 32). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev ...

Page 32

... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 21 on page 33. Data either the last of a burst of two or the last desired element of a longer burst. The 128Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2 ...

Page 33

... Figure 21: WRITE-to-WRITE COMMAND ADDRESS Notes: 1. DQM is LOW. Each WRITE command may be to any bank. Figure 22: Random WRITE Cycles COMMAND ADDRESS PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev CLK WRITE NOP WRITE BANK, BANK, COL n COL b ...

Page 34

... BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied 1 clock previous to the BURST TERMINATE command. This is shown in Figure 25 on page 35, where data n is the last desired data element of a longer burst. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev CLK ...

Page 35

... DQM COMMAND ADDRESS Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Figure 25: Terminating a WRITE Burst COMMAND ADDRESS Notes: 1. DQMs are LOW. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev CLK WRITE NOP PRECHARGE BANK BANK all) COL n ...

Page 36

... The device may not remain in the power-down state longer than the refresh period ( performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev RP) after the PRECHARGE command is issued. HIGH All Banks Bank Selected ...

Page 37

... Figure 28 and Figure 29 on page 38.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Figure 28: Clock Suspend During WRITE Burst INTERNAL CLOCK COMMAND ADDRESS PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev CKS ...

Page 38

... Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. ...

Page 39

... WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 32 on page 40). PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev ...

Page 40

... DQM is LOW. Figure 33: WRITE With Auto Precharge Interrupted by a WRITE CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Notes: 1. DQM is LOW. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev met, where WR begins when the WRITE to bank m is registered. The last WRITE - AP READ - AP NOP NOP BANK n ...

Page 41

... H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...

Page 42

... Allowable commands to the other bank are determined by its current state and Truth Table 3 and according to Truth Table 4. Precharging: Row activating: Read w/auto precharge enabled: Write w/auto precharge enabled: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN CAS# WE# Command (Action COMMAND INHIBIT (NOP/continue previous operation ...

Page 43

... RC is met, the SDRAM will be in the all banks idle state. Starts with registration of a LMR command and ends when t has been met. After MRD is met, the SDRAM will be in the all banks idle state. Starts with registration of a PRECHARGE ALL command and ends t t when RP is met ...

Page 44

... Read: Write: Read w/auto precharge enabled: Write w/auto precharge enabled: 4. AUTO REFRESH, SELF REFRESH, and LMR commands may only be issued when all banks are idle. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN CAS# WE# Command (Action COMMAND INHIBIT (NOP/continue previous operation OPERATION (NOP/continue previous operation) ...

Page 45

... WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to bank n will begin after tered. The last valid WRITE to bank n will be data registered 1 clock prior to the WRITE to bank m (Figure 33 on page 40). PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 128Mb: x4, x8, x16 SDRAM met, where WR begins when the WRITE to bank m is regis- Micron Technology, Inc ...

Page 46

... Storage temperature (plastic) Power dissipation Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Table 12 on page 47, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’ ...

Page 47

... For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as typical. 3. These are estimates; actual results may vary. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Symbol ...

Page 48

... Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 35: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point Figure 36: Example Temperature Test Point Location, 60-Ball FBGA: Top View Test point PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 22.22mm 11.11mm 8.00mm 4.00mm 8.00mm 4.00mm 8.00mm 4.00mm 16 ...

Page 49

... Note: 2; notes appear on page 51 Parameter – TSOP “TG” Package Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQ Parameter – FBGA “FB” Input capacitance: CLK Input capacitance: All other input-only pins PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev +3.3 ±0. Symbol ...

Page 50

... Table 18: AC Functional Characteristics Notes 11; notes appear on page 51 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN -6A -7E Symbol Min Max Min t AC(3) – ...

Page 51

... High-Z. 11. AC timing and I crossover point. If the input transition time is longer than 1 ns, then the timing is ref- erenced at V should always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09 for more details. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Symbol t DQM t DQZ t ...

Page 52

... CKE is HIGH during refresh command period limit is actually a nominal value and does not result in a fail value. 34. PC133 specifies a minimum of 2.5pF. 35. PC133 specifies a minimum of 2.5pF. 36. PC133 specifies a minimum of 3.0pF. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev levels specifications are tested after the device is properly initialized. ...

Page 53

... CLK stable Notes CS# is HIGH at clock HIGH time, all commands applied are NOP. 2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. 3. JEDEC and PC100 specify 3 clocks. 4. Outputs are guaranteed High-Z after command is issued. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev ...

Page 54

... High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode Notes: 1. Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev CKS NOP NOP Input buffers gated off while in power-down mode ...

Page 55

... A0–A9, A11 COLUMN A10 BA0, BA1 BANK DQ Notes: 1. For this example and auto precharge is disabled. 2. x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev NOP NOP NOP OUT OUT t LZ Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 56

... COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all active banks Notes: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev AUTO NOP ...

Page 57

... BA0, BA1 BANK(S) High Precharge all active banks Notes maximum time limit for self refresh XSR requires minimum of 2 clocks regardless of frequency or timing. 3. Self refresh mode not supported on automotive temperature (AT) devices. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev CKS ≥ t RAS min ...

Page 58

... BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev READ NOP NOP t CMS t CMH ...

Page 59

... ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev READ NOP NOP t CMS t CMH COLUMN m 2 BANK ...

Page 60

... DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” 3. PRECHARGE command not allowed or PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev READ NOP ...

Page 61

... BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” 3. READ command not allowed or PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Auto Precharge NOP 2 NOP 2 READ t CMS t CMH ...

Page 62

... BANK RCD - BANK 0 t RAS - BANK BANK 0 t RRD Notes: 1. For this example and x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev READ NOP ACTIVE t CMS t CMH COLUMN m 2 ROW ROW ...

Page 63

... A0–A9, A11 ROW ROW A10 BA0, BA1 BANK DQ t RCD Notes: 1. For this example x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” 3. Page left open; no PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev READ NOP NOP NOP t CMH BANK ...

Page 64

... A10 DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD Notes: 1. For this example and x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev READ NOP NOP t CMS t CMH COLUMN m 2 BANK t AC ...

Page 65

... RAS t RC Notes: 1. For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns is required between <D quency. 3. x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev WRITE NOP NOP ...

Page 66

... A0–A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK RCD t RAS t RC Notes: 1. For this example x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev WRITE NOP NOP NOP t CMH BANK ...

Page 67

... RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns is required between <D 3. x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev NOP 2 NOP 2 WRITE ...

Page 68

... AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” 3. Write command not allowed or PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev NOP 3 NOP 3 WRITE NOP t CMS t CMH COLUMN m 2 ...

Page 69

... BA0, BA1 BANK RCD - BANK 0 t RAS - BANK BANK 0 t RRD Notes: 1. For this example x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev WRITE NOP ACTIVE NOP t CMH ROW ROW BANK 0 BANK 1 ...

Page 70

... AH BA0, BA1 BANK DQ t RCD Notes: 1. x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” must be satisfied prior to PRECHARGE command. 3. Page left open; no PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev WRITE NOP NOP t CMH t CMS COLUMN m 1 BANK ...

Page 71

... AH ROW A10 BA0, BA1 BANK DQ t RCD Notes: 1. For this example x16: A9 and A11 = “Don’t Care.” x8: A11 = “Don’t Care.” PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev NOP WRITE NOP t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE ...

Page 72

... All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. “2X” means the notch is present in two locations (both ends of the device). PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 22.22 ±.08 2X 0.71 2X 0.10 2.80 +0 ...

Page 73

... Notes: 1. All dimensions in millimeters. 2. Recommended pad size for PCB is 0.33mm ±0.025mm. 3. Topside part marking decoder can be found at http://www.micron.com/decoder. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 0.10 A SEATING PLANE 2.40 ±0.05 A CTR 8.00 ±0.10 5.60 BALL #1 ID ...

Page 74

... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 6.40 0.80 TYP ...

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