ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet
ST72T774J9B1
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ST72T774J9B1 Summary of contents
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USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I User ROM/OTP/EPROM Kbytes Data RAM Kbytes (256 bytes stack) 8 MHz Internal Clock ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72774/ST727754/ST72734 5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision follow-up Changes applied since version 4.0 Version 4.0 March 2001 Page 1:Addition of 72T774 (32KOTP). Addition of 60K/48K ROM for ST72754 Deletion of table “ device summary”, replaced with cross reference to table 36 on page 147. page 13 ...
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ST72774/ST727754/ST72734 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72774, ST72754 and ST72734 are HCMOS microcontroller units (MCU) from the ST727x4 family with dedicated peripherals for Monitor applications. They are based around an industry standard 8-bit core and offer an enhanced instruction ...
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PIN DESCRIPTION Figure 2. 44-pin TQFP and 42-Pin SDIP Package Pinouts PWM7 / PC6 PWM8 / PC7 PWM2 / AIN3 / PB7 PWM1 / AIN2 / PB6 AIN1 / PB5 AIN0 / PB4 USBVCC USBDM USBDP HSYNCDIV / PC0 ...
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ST72774/ST727754/ST72734 PIN DESCRIPTION (Cont’d) RESET: Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered low. It ...
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Pin No. Pin Name Type 18 23 PD3/VFBACK/ITA I PD4/ITB I PD5/HFBACK I PD6/CLAMPOUT I PB0/SCLD I PB1/SDAD I PB2/SCLI I PB3/SDAI I PA7/BLANKOUT ...
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ST72774/ST727754/ST72734 1.3 MEMORY MAP Figure 3. Memory Map 0000h HW Registers (see 005Fh 0060h 1 Kbyte RAM 03FFh 0400h Reserved 0FFFh 1000h 60 Kbytes 4000h 48 Kbytes 8000h 32 Kbytes FFDFh FFE0h Interrupt & Reset Vectors * (see FFFFh any ...
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MEMORY MAP (Cont’d) Table 2. Hardware Register Memory Map Address Block Register Label 0000h PADR 0001h PADDR 0002h PBDR 0003h PBDDR 0004h PCDR 0005h PCDDR 0006h PDDR 0007h PDDDR 0008h Watchdog WDGCR 0009h MISCR 000Ah ADCDR ADC 000Bh ADCCSR 000Ch ...
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ST72774/ST727754/ST72734 Address Block Register Label 0025h USBPIDR 0026h USBDMAR 0027h USBIDR 0028h USBISTR 0029h USBIMR 002Ah USBCTLR 002Bh USB USBDADDR 002Ch USBEP0RA 002Dh USBEP0RB 002Eh USBEP1RA 002Fh USBEP1RB 0030h USBEP2RA 0031h USBEP2RB 0032h PWM1 0033h BRM21 0034h PWM2 0035h PWM3 ...
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Address Block Register Label 0050h DDCCR 0051h DDCSR1 0052h DDCSR2 0053h DDC/CI 0054h DDCOAR 0055h 0056h DDCDR 0057h 0058h 0059h I2CDR 005Ah 005Bh 005Ch I2C I2CCCR 005Dh I2CSR2 005Eh I2CSR1 005Fh I2CCR Table 3. Interrupt Vector Map Vector Address FFE0-FFE1h ...
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ST72774/ST727754/ST72734 1.4 External connections The following figure shows the recommended ex- ternal connections for the device. The V pin is only used for programming OTP PP and EPROM devices and must be tied to ground in user mode. The 10 ...
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CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit ...
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ST72774/ST727754/ST72734 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This ...
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CPU REGISTERS (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is always pointing to the next free location in ...
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ST72774/ST727754/ST72734 3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a crystal or an external clock signal to drive the internal oscillator. The internal clock (CPU CLK running at f derived ...
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CLOCK SYSTEM (Cont’d) 3.1.2 Crystal Resonator The internal oscillator is designed to operate with an AT-cut parallel resonant resonator in the frequency range specified for f The circuit shown in Figure 8 when using a crystal, Recommended Crystal Values,” on ...
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ST72774/ST727754/ST72734 3.2 RESET The Reset procedure is used to provide an orderly software start- quit low power modes. Five conditions generate a reset: LVD, watchdog, external pulse at the RESET pin, illegal address, illegal opcode. A reset causes ...
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RESET (Cont’d) Figure 10. Low Voltage Detector Functional Diagram Figure 11. LVD Reset Signal Output RESPOF LVD V DD RESET FROM WATCHDOG RESET Figure 12. Reset Timing Diagram t DDR V DD OSCIN t OXOV f CPU PC RESET WATCHDOG ...
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ST72774/ST727754/ST72734 3.3 INTERRUPTS The ST727x4 may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 6 and a non-maskable software interrupt (TRAP). The Interrupt flowchart is shown in Figure 13. The maskable interrupts must ...
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INTERRUPTS (Cont’d) Figure 13. Interrupt Processing Flowchart EXECUTE INSTRUCTION RESTORE PC FROM STACK FROM RESET Y TRAP BIT SET? Y FETCH NEXT INSTRUCTION N IRET? Y THIS CLEARS I BIT BY DEFAULT ST72774/ST727754/ST72734 N ...
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ST72774/ST727754/ST72734 INTERRUPTS (Cont’d) Table 6. Interrupt Mapping Source Description Block RESET Reset TRAP Software USB End Suspend Interrupt DDC/CI DDC/CI Interrupt DDC1/2B DDC1/2B Interrupt Port D bit 4 External Interrupt ITB Port D bit 3 External Interrupt ITA Input Capture ...
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POWER SAVING MODES 3.4.1 WAIT Mode This mode is a low power consumption mode. The WFI instruction places the MCU in WAIT mode: The internal clock remains active but all CPU processing is stopped; however, peripherals are still running. ...
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ST72774/ST727754/ST72734 3.5 MISCELLANEOUS REGISTER MISCELLANEOUS REGISTER (MISCR) Address: 0009h — Read/Write Reset Value: 0001 0000 (10h) 7 VSYNC FLY_S HSYNC FAST ITBLAT ITALAT ITBITE ITAITE SEL YN DIVEN Bit 7= VSYNCSEL DDC1 VSYNC Selection. This bit is set and cleared ...
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ON-CHIP PERIPHERALS 4.1 I/O PORTS 4.1.1 Introduction The I/O ports allow the transfer of data through digital inputs and outputs, and, for specific pins, the input of analog signals or the Input/Output of alternate signals for on-chip peripherals (DDC, ...
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ST72774/ST727754/ST72734 I/O PORTS (Cont’d) Table 7. I/O Pin Functions DDR 0 1 4.1.2 Common Functional Description Each port pin of the I/O Ports can be individually configured under software control as either input or output. Each bit of a Data ...
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Figure 16. Input Structure for SYNC signals TTL trigger Pin (no pull-up) I/O logic (if existing pull-up TTL trigger Pin I/O logic (if existing) 4.1.3 Port A PA7 and PA[2:0] can be defined as Input lines (with pull-up) ...
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ST72774/ST727754/ST72734 I/O PORTS (Cont’d) Figure 17. PA0 to PA2, PA7 DR latch DDR latch DDR SEL DR SEL Figure 18. PA3 to PA6 DR latch DDR latch DDR SEL DR SEL Alternate input 30/144 Alternate enable 1 Alternate output 0 ...
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I/O PORTS (Cont’d) 4.1.4 Port B The alternate functions are the I/O pins of the on- chip DDC SCLD & SCDAD for PB0:1, the I/O pins of the on-chip I2C SCLI & SCDAI for PB2:3, and 4 bits of port ...
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ST72774/ST727754/ST72734 I/O PORTS (Cont’d) Figure 19. PB0 to PB3 DR latch DDR latch DDR SEL DR SEL Alternate input Figure 20. PB4 to PB7 DR latch DDR latch DDR SEL DR SEL DR SEL 32/144 Alternate enable 1 Alternate output ...
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I/O PORTS (Cont’d) 4.1.5 Port C The available port pins of port C may be used as general purpose I/O. Table 10. Port C Description PORT C Input* PC0 With pull-up PC1 With pull-up PC2 With pull-up ...
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ST72774/ST727754/ST72734 I/O PORTS (Cont’d) Figure 21. PC0, PC2 to PC7 DDR SEL DR SEL Figure 22. PC1 DDR SEL DR SEL AV 34/144 Alternate enable 1 Alternate output 0 DR latch OC1E DDR latch latch DDR latch ...
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I/O PORTS (Cont’d) 4.1.6 Port D The Port D I/O pins are normally used for the input and output of video synchronization signals of the Sync Processor, but are set to I/O Input with pull- up upon reset. The I/O ...
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ST72774/ST727754/ST72734 I/O PORTS (Cont’d) Figure 23. PD2 to PD5 DDR SEL DR SEL alternate input CSYNCI Input HFBACK Input VFBACK Input Figure 24. PD0 to PD1 DDR SEL DR SEL Alternate input 36/144 DR latch DDR latch 1 0 TTL ...
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I/O PORTS (Cont’d) Figure 25. PD6 DDR SEL DR SEL Alternate input VSYNCI2 input Alternate enable 1 Alternate output 0 DR latch Alternate enable DDR latch 1 0 TTL Schmitt Trigger ST72774/ST727754/ST72734 V DD P-BUFFER PULL-UP N-BUFFER Alternate enable V ...
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ST72774/ST727754/ST72734 I/O PORTS (Cont’d) 4.1.7 Register Description Data Registers (PxDR) Read /Write Reset Value: 0000 0000 (00h) 7 MSB Table 12. I/O Ports Register Map Address Register 7 Name (Hex.) 00 PADR MSB 01 PADDR MSB 02 PBDR MSB 03 ...
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WATCHDOG TIMER (WDG) 4.2.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The ...
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ST72774/ST727754/ST72734 Table 13. Watchdog Timing (f CR Register WDG timeout period initial value Max FFh Min C0h Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be ...
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TIMER (TIM) 4.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals ( input ...
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ST72774/ST727754/ST72734 16-BIT TIMER (Cont’d) Figure 27. Timer Block Diagram CPU CLOCK 8 low 8 high 8-bit buffer EXEDG 16 BIT 1/2 FREE RUNNING 1/4 COUNTER 1/8 COUNTER ALTERNATE REGISTER CC1 CC0 OVERFLOW EXTCLK DETECT CIRCUIT ICF1 OCF1 TOF ICF2 ICIE ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MSB At t0 Other instructions Returns the buffered Read LSB At t0 +Dt LSB value at t0 Sequence completed ...
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ST72774/ST727754/ST72734 16-BIT TIMER (Cont’d) Figure 28. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 29. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...
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TIMER (Cont’d) 4.3.3.3 Input Capture In this section, the index may The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a ...
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ST72774/ST727754/ST72734 16-BIT TIMER (Cont’d) Figure 31. Input Capture Block Diagram ICAP1 EDGE DETECT CIRCUIT2 ICAP2 IC2R 16-BIT 16-BIT FREE RUNNING COUNTER Figure 32. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive edge is ...
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TIMER (Cont’d) 4.3.3.4 Output Compare In this section, the index may This function can be used to control an output waveform or indicating when a period of time has elapsed. When a match ...
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ST72774/ST727754/ST72734 16-BIT TIMER (Cont’d) Figure 33. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC2R OC1R Figure 34. Output Compare Timing Diagram, Internal Clock Divided by 2 INTERNAL CPU CLOCK OUTPUT COMPARE REGISTER ...
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TIMER (Cont’d) 4.3.3.5 Forced Compare Mode In this section i may represent The following bits of the CR1 register are used: FOLV2 FOLV1 OLVL2 When the FOLV i bit is set, the OLVL i bit is ...
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ST72774/ST727754/ST72734 16-BIT TIMER (Cont’d) 4.3.3.7 Pulse Width Modulation Mode Pulse Width Modulation mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation mode ...
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Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER ...
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ST72774/ST727754/ST72734 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Enable. 0: Output Compare 1 function is enabled, but the ...
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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...
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ST72774/ST727754/ST72734 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 (OC2LR) ...
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TIMER (Cont’d) Table 16. 16-Bit Timer Register Map Address Register 7 Name (Hex.) 11 CR2 OC1E 12 CR1 ICIE 13 SR ICF1 14 IC1HR MSB 15 IC1LR MSB 16 OC1HR MSB 17 OC1LR MSB 18 CHR MSB 19 CLR ...
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ST72774/ST727754/ST72734 4.4 SYNC PROCESSOR (SYNC) 4.4.1 Introduction The Sync processor handles all the management tasks of the video synchronization signals, and is used with the timer and software to provide information and status on the video standard and timings. This ...
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SYNC PROCESSOR (SYNC) (Cont’d) 4.4.3 Input Signals The Sync Processor has the following inputs (TTL level): – VSYNCI1 Vertical Sync input1 – HSYNCI1 Horizontal Sync input1 or Composite sync – VSYNCI2 Vertical Sync input2 – HSYNCI2 Horizontal Sync input2 or ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) Figure 38. Typical Horizontal Sync Input Timing or: Maximum Sync. pulse width: 7µs Note: Minimum HPeriod: 500ns + S/W interrupt servicing time (1 Timer Clock) Figure 39. Vertical Sync Input Timing or: Typical Sync. pulse ...
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SYNC PROCESSOR (SYNC) (Cont’d) ClampOut and Moire Signal Clamp Output signal The clamping pulse generator can control the pulse width and polarity signal and can be configured as pseudo-front porch or back porch. To use the ClampOut signal: – Select ...
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ST72774/ST727754/ST72734 Figure 41. Moire Output (instead of Clamping Output) VFBACK HFBACK Moire 4.4.5.1 Blanking output signal The Video Blanking function uses VSYNCO, HFBACK, VFBACK as input BLANKOUT output as Video Blanking Output. This output pin open-drain output ...
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SYNC PROCESSOR (SYNC) (Cont’d) 4.4.6 Input Processing 4.4.6.1 Detecting Signal Presence The Sync Processor provides two ways of checking input signal presence, by directly polling the LATR Latch Register or using the Timer interrupts. Polling check Use the Latch Register ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) 4.4.6.3 Detecting Signal Polarity The Sync Processor provides two ways for checking input signal polarity by polling the latches or using the 5-bit up/down counter. Polling check – HSYNCI polarity detection: UPLAT/DWNLAT bits in LATR ...
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SYNC PROCESSOR (SYNC) (Cont’d) 4.4.6.5 Example of VSYNCO extraction for a negative composite sync with serration pulses Refer to Figure 43. In extraction mode, the 5-bit comparator checks the counter value with respect to the threshold. When the incoming signal ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) 4.4.7 Output Processing 4.4.7.1 Generating Free-Running Frequencies The free-running frequencies function is used to: – Drive the monitor when no or bad sync signals are received. – Stabilize the OSD screen when the monitor is ...
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SYNC PROCESSOR (SYNC) (Cont’d) 4.4.8 Analyzer Mode The analyzer block is used for all extra measurements on the sync signals to manage the monitor functions: – Measure the number of scan lines per frame (VSYNCO or VFBACK) to simplify the ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) 4.4.8.2 Vertical Output Measurement The function of vertical pulse measurement is to: – Capture the number of HSYNCO pulses during a Low level of VSYNCO. – Capture the number of HFBACK pulses during a Low ...
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SYNC PROCESSOR (SYNC) (Cont’d) 4.4.9 Corrector Mode In this mode, you can perform the following functions: – Inhibit pre/post equalization pulses This removes all pre/post equalization pulses on the HSYNCO signal. The inhibition starts on the falling edge of HSYNCO ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) 4.4.10 Register Description CONFIGURATION REGISTER (CFGR) Read/Write Reset Value: 0000 0000 (00h) 7 HACQ VACQ - 2FHINH VEXT Bit 7 = HACQ Horizontal Sync Analyzer Mode Set by software, reset by hardware when the measurement ...
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SYNC PROCESSOR (SYNC) (Cont’d) MUX CONTROL REGISTER (MCR) Read/Write Reset Value: 0010 0000 (20h) 7 BP1 BP0 FBSEL SCI0 HS1 Bit 7:6 = BP1, BP0 Back Porch Pulse control BP1 BP0 Back Porch pulse width Back Porch, ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) COUNTER CONTROL REGISTER (CCR) Read/Write Reset Value: 0000 0000 (00h) 7 PSCD LCV1 LCV0 CV4 CV3 CV2 CV1 CV0 Bit 7 = PSCD Prescaler Enable bit. 0: Enable the Prescaler by 256 1: Disable the ...
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SYNC PROCESSOR (SYNC) (Cont’d) LATCH REGISTER (LATR) Read/Write Reset Value: 0000 0000 (00h) 7 CSYN HSYN VSYN HFLY VFLY UPLAT DWNLAT 2FHLAT Bit 7 = CSYN Detection of pulses on CSYNCI Set on falling edge of CSYNCI Cleared by software ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) HORIZONTAL SYNC GENERATOR REGISTER (HGENR) Read/Write Reset Value: 0000 0000 (00h) 7 MSB Case HVGEN = 1: Generation mode In this mode, this register contains the Hsync free- running frequency. The generated signal is: - ...
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SYNC PROCESSOR (SYNC) (Cont’d) ENABLE REGISTER (ENR) Read/Write Reset Value: 1100 0011 (C3h) 7 SYNOP CLMPEN BLKEN HVGEN 2FHEN HINH HSIN1 VSIN1 Bit 7 = SYNOP HSYNCO, VSYNCO outputs enable 0: Enabled 1: Disabled Bit 6 = CLMPEN Clamping or ...
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ST72774/ST727754/ST72734 SYNC PROCESSOR (SYNC) (Cont’d) Table 21. SYNC Register Map and Reset Values Address Register 7 Name (Hex.) CFGR HACQ 40 Reset Value 0 MCR BP1 41 Reset Value 0 CCR PSCD 42 Reset Value 0 POLR SOG 43 Reset ...
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TIMING MEASUREMENT UNIT (TMU) 4.5.1 Introduction The timing measurement unit (TMU) allows the analysis of the current video timing characteristics in order to control display position and size. It consists of measuring the timing between the horizontal or vertical ...
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ST72774/ST727754/ST72734 TIMING MEASUREMENT UNIT (Cont’d) – Obtain the minimum number of horizontal sync output pulses (V2) between the last fall- ing edge of the active video input (AV) and the rising edge of the vertical sync signal (VSYN ...
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TIMING MEASUREMENT UNIT (Cont’d) 4.5.4 Register Description CONTROL STATUS REGISTER (TMUCSR) Bit 7:2 - Read only Bit 1:0 - Read/Write Reset Value: 1111 1100 (FCh) 7 T2[10] T2[9] T2[8] T1[10] T1[9] T1[8] Bit 7:5 = T2[10:8] MSB of T2 Counter. ...
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ST72774/ST727754/ST72734 TIMING MEASUREMENT UNIT (Cont’d) Table 22. TMU Register Map and Reset Values Address Register 7 Name (Hex.) T2[10] CSR 0E Reset Value 1 T1CR T1[7] 0F Reset Value 1 T2CR T2[7] 10 Reset Value 1 78/144 ...
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USB INTERFACE (USB) 4.6.1 Introduction The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components ...
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ST72774/ST727754/ST72734 USB INTERFACE (Cont’d) 4.6.4 Register Description DMA ADDRESS REGISTER (DMAR) Read / Write Reset Value: Undefined 7 DA15 DA14 DA13 DA12 DA11 Bits 7:0=DA[15:8] DMA address bits 15-8. See the description of bits DA7-6 in the next register (IDR). ...
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USB INTERFACE (Cont’d) PID REGISTER (PIDR) Read only Reset Value: xx00 0000 (x0h) 7 TP3 TP2 Bits 7:6 =TP3-TP2 Token PID bits 3 & USB token PIDs are encoded in four bits. TP3-TP2 correspond to ...
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ST72774/ST727754/ST72734 USB INTERFACE (Cont’d) Bit 0 = SOF Start of frame. This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on the USB bus SOF signal detected 1: SOF signal detected Note: ...
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USB INTERFACE (Cont’d) ENDPOINT n REGISTER A (EPnRA) Read / Write Reset Value: 0000 xxxx (0xh) 7 ST_ DTOG STAT STAT TBC OUT _TX _TX1 _TX0 3 These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They ...
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ST72774/ST727754/ST72734 USB INTERFACE (Cont’d) ENDPOINT n REGISTER B (EPnRB) Read / Write Reset Value: 0000 xxxx (0xh) 7 DTOG STAT STAT CTRL EA3 _RX _RX1 _RX0 These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 ...
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USB INTERFACE (Cont’d) 4.6.5 Programming Considerations In the following, the interaction between the USB interface and the application program is described. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events ...
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ST72774/ST727754/ST72734 USB INTERFACE (Cont’d) Table 23. USB Register Map and Reset Values Address Register 7 Name (Hex.) PIDR TP3 25 Reset Value x DMAR DA15 26 Reset Value x IDR DA7 27 Reset Value x ISTR SUSP 28 Reset Value ...
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I²C SINGLE MASTER BUS INTERFACE (I2C) 4.7.1 Introduction 2 The I C Bus Interface serves as an interface between the microcontroller and the serial I It provides single master functions, and controls all bus-specific sequencing, protocol ...
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ST72774/ST727754/ST72734 I²C SINGLE MASTER BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The speed of the I C interface may be selected between Standard (0-100KHz) and Fast I 400KHz). SDA/SCL Line Control Transmitter mode: the interface ...
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I²C SINGLE MASTER BUS INTERFACE (Cont’d) 4.7.4 Functional Description (Master Mode) Refer to the CR, SR1 and SR2 registers in 4.7.5. for the bit definitions default the I C interface operates in idle mode (M/IDL bit is cleared) ...
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ST72774/ST727754/ST72734 I²C SINGLE MASTER BUS INTERFACE (Cont’d) Figure 54. Transfer Sequencing Master receiver: S Address A EV1 EV2 Master transmitter: S Address A EV1 EV2 EV4 Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, SB=1, cleared ...
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I²C SINGLE MASTER BUS INTERFACE (Cont’d) 4.7.5 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h START ACK Bit 7:6 = Reserved. Forced hardware. Bit ...
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ST72774/ST727754/ST72734 I²C SINGLE MASTER BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF 0 TRA 0 BTF Bit 7 = EVF Event flag. This bit is set by hardware as ...
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I²C SINGLE MASTER BUS INTERFACE (Cont’ STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h Bit 7:5 = Reserved. Forced hardware. Bit Acknowledge ...
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ST72774/ST727754/ST72734 I2C SINGLE MASTER BUS INTERFACE (Cont’d) 2 Table 24 Register Map Address Register 7 Name (Hex Reset Value 0 SR1 EVF 5E Reset Value 0 SR2 5D Reset Value 0 CCR FM/SM 5C Reset Value ...
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DDC INTERFACE (DDC) 4.8.1 Introduction The DDC (Display Data Channel) Bus Interface is mainly used by the monitor to identify itself to the video controller, by the monitor manufacturer to perform factory alignment, and by the user to adjust ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) Figure 57. DDC Interface Block Diagram SDAD DATA CONTROL SCLD VSYNCI VSYNCI2 DDC1/2B (for MONITOR IDENTIFICATION) Bit in MISCR Register DDC/CI-Factory CONTROL REGISTER (CR) (DDC/CI (for MONITOR ADJUSTMENT and CONTROL) 96/144 ADDRESS LOW REGISTER (ALR) ADDRESS ...
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DDC INTERFACE (Cont’d) 4.8.3 Signal Description Serial Data (SDA) The SDA bidirectional pin is used to transfer data in and out of the device open-drain output that may be or-wired with other open-drain or open-collector pins. An ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) 2 4.8 BUS Protocol 2 A standard I C communication is normally based on four parts: START condition, device slave address transmission, data transfer and STOP condition. They are described brielfly in the following ...
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DDC INTERFACE (Cont’d) 4.8.5 DDC Standard The DDC standard is divided in several data transfer protocols: DDC1, DDC2B, DDC/CI. For DDC1/2B, refer to the “VESA DDC Standard v3.0” specification. For DDC/CI refer to the “VESA DDC Commands Interface v1.0” – ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) The Write and Read operations allow the EDID data to be downloaded during factory alignment (for example). Writes to the memory by the DMA engine can be inhibited by means of the WP bit in the ...
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DDC INTERFACE (Cont’d) Figure 60. Mapping of DDC1 data structure FFFFh 128-byte Data Structure 0000h FFFFh 128-byte Data Structure Reserved 0000h DDC2B Transition Mode: This mode avoids the display switching to DDC2B mode if spurious noise is detected on SCL ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) DDC2B Mode: The DDC1/2B Interface enters DDC2B mode either from the transition state or from the initial state if software sets the HWPE bit while P&D only or FPDI-2 mode is selected. Once in DDC2B mode, ...
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Figure 63. DDC1/2B Operation Flowchart Wait for HWPE = 1 Relative Address (ALR Vsync Counter = 0 Start 2-sec Timer Received valid Device Address? Vsync Counter += 1 Counter = 128 N or Timer expired ? HWPE ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) EDID Data structure mapping: An internal address pointer defines the memory location being addressed made of two 8-bit registers AHR and ALR. AHR is initialized by software. It defines the 256- byte block within ...
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DDC INTERFACE (Cont’d) Write Operation Once the DDC1/2B Interface has acknowledged a write transfer request, i.e. a Device Address with RW=0, it waits for a data address. When the latter is received acknowledged and loaded into the ALR. ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) Figure 66. Read sequences Addr. Pointer DEV ADDR SDA Addr. Pointer DEV ADDR SDA Addr. Pointer DEV ADDR SDA 106/144 CURRENT ADDRESS READ ADDR ADDR + 1 DATA OUT RANDOM ADDRESS READ XXXXh DEV ADDR DATA ...
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DDC INTERFACE (Cont’d) 4.8.5.2 DDC/CI - Factory Alignment Interface 4.8.5.2.1 Functional Description Refer to the CR, SR1 and SR2 registers in 4.8.6. for the bit definitions. The DDC/CI interface works as an I/O interface between the microcontroller and the DDC2Bi, ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte, the following events ...
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DDC INTERFACE (Cont’d) Figure 67. Transfer Sequencing Slave receiver: S Address A Data1 EV1 Slave transmitter: S Address A Data1 EV1 EV3 Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading SR1 register. ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) 4.8.6 Register Description DDC CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h) 7 EDDC Bit 7:6 = Reserved. Forced hardware. Bit Peripheral ...
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DDC INTERFACE (Cont’d) DDC STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF 0 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) DDC STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h STOPF Bit 7:5 = Reserved. Forced hardware. Bit Acknowledge failure . This bit ...
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DDC INTERFACE (Cont’d) DDC DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h Bit 7:0 = D7-D0 8-bit Data Register. These bits contain the byte to be received or transmitted on the ...
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ST72774/ST727754/ST72734 DDC INTERFACE (Cont’d) DDC1/2B CONTROL REGISTER (DCR) Read / Write Reset Value: 0000 0000 (00h CF2 EDF EDE CF1 Bit 7 = Reserved. Forced by hardware to 0. Bit 5 = EDF End of Download interrupt Flag ...
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DDC INTERFACE (Cont’d) Table 26. DDC Register Map and Reset Values Address Register 7 Name (Hex Reset Value 0 SR1 EVF 51 Reset Value 0 SR2 52 Reset Value 0 OAR ADD7 54 Reset Value ...
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ST72774/ST727754/ST72734 4.9 PWM/BRM GENERATOR (DAC) 4.9.1 Introduction This PWM/BRM peripheral includes two types of PWM/BRM outputs, with differing step resolutions based on the Pulse Width Modulator (PWM) and Binary Rate Multiplier (BRM) Generator technique are available. It allows the digital ...
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PWM/BRM Outputs (Cont’d) PWM/BRM Outputs The PWM/BRM outputs are assigned to dedicated pins. The RC filter time must be higher than TCPUx64. Figure 70. Typical PWM Output Filter OUTPUT STAGE Figure 71. PWM Simplified Voltage Output After Filtering V DD ...
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ST72774/ST727754/ST72734 PWM/BRM GENERATOR (Cont’d) BRM Generation The BRM bits allow the addition of a pulse to widen a standard PWM pulse for specific PWM cycles. This has the effect of “fine-tuning” the PWM Duty cycle (without modifying the base duty ...
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PWM/BRM GENERATOR (Cont’d) Figure 73. Simplified Filtered Voltage Output Schematic with BRM added VDD PWMOUT 0V VDD OUTPUT VOLTAGE 0V Figure 74. Graphical Representation of 4-Bit BRM Added Pulse Positions BRM VALUE 0001 bit0=1 0001 bit0=1 0100 ...
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ST72774/ST727754/ST72734 PWM/BRM GENERATOR (Cont’d) 4.9.3.2 PWM/BRM OUTPUTS The PWM/BRM outputs are assigned to dedicated pins. If necessary, these pins can be used in push-pull or open-drain modes under software control. In these pins, the PWM/BRM outputs are connected to a ...
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PWM/BRM GENERATOR (Cont’d) 4.9.4 Register Description 4.9.4.1 PWM/BRM REGISTERS On a channel basis, the 10 bits are separated into two data registers: – A 6-bit PWM register corresponding to the binary weight of the PWM pulse. – A 4-bit BRM ...
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ST72774/ST727754/ST72734 Table 29. PWM Register Map Address Register 7 Name (Hex.) 32 PWM1 33 BRM21 34 PWM2 35 PWM3 36 BRM43 37 PWM4 38 PWM5 39 BRM65 3A PWM6 3B PWM7 3C BRM87 3D PWM8 3E PWMCR 122/144 6 5 ...
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A/D CONVERTER (ADC) 4.10.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device ...
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ST72774/ST727754/ST72734 4.10.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage ( greater than ...
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A/D CONVERTER (ADC) (Cont’d) 4.10.6 Register Description CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by ...
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ST72774/ST727754/ST72734 5 INSTRUCTION SET 5.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld ...
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ST7 ADDRESSING MODES (Cont’d) 5.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For Interrupt ...
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ST72774/ST727754/ST72734 The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 5.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed ...
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INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and ...
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ST72774/ST727754/ST72734 INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2’s compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry ...
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ST72774/ST727754/ST72734 6 ELECTRICAL CHARACTERISTICS The ST727x4 device contains circuitry to protect the inputs against damage due to high static voltage or electric field. Nevertheless it is advised to take normal precautions and to avoid applying to this high impedance voltage ...
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POWER CONSIDERATIONS The average chip-junction temperature, T degrees Celsius, may be calculated using the following equation Where: – the Ambient Temperature – ...
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ST72774/ST727754/ST72734 6.2 AC/DC ELECTRICAL CHARACTERISTICS ( +70°C unless otherwise specified) A Symbol Parameter V Operating Supply Voltage DD CPU RUN mode CPU WAIT mode I DD CPU HALT mode (see Note 1) USB Suspend mode (see Note ...
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AC/DC ELECTRICAL CHARACTERISTICS (Cont’d) Symbol Parameter Output Low Level Voltage Port A[7,2:0], Port B[7:4 Port C[7:0], Port D[6:0] Push Pull Output Low Level Voltage Port A[6: Open Drain Output Low Level Voltage V OL Port A ...
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ST72774/ST727754/ST72734 AC/DC ELECTRICAL CHARACTERISTICS (Cont’d) Symbol Parameter f Analog control frequency ADC |TUE| Total unadjusted error OE Offset error GE Gain error |DLE| Differential linearity error |ILE| Integral linearity error V Conversion range voltage AIN I A/D conversion supply current ...
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AC/DC ELECTRICAL CHARACTERISTICS (Cont’d) Parameter Hysteresis of Schmitt trigger inputs Fixed input levels V -related input levels DD Pulse width of spikes which must be sup- pressed by the input filter Output fall time from VIH min to VIL max ...
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ST72774/ST727754/ST72734 Parameter Inputs Levels: Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High USBVCC: voltage level Notes: – the load connected on the USB drivers. – All the ...
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GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 79. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width Figure 80. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width ST72774/ST727754/ST72734 Dim ...
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ST72774/ST727754/ST72734 Figure 81. 44-Pin Thin Quad Flat Package 140/144 0.10mm .004 seating plane inches Dim Min Typ Max Min Typ Max A 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 ...
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... ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics. 8.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options (if any). The ROM contents are to be sent on diskette electronic means, with the hexadecimal file in .S19 format generated by the development tool ...
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... ST72774/ST727754/ST72734 Table 36. Ordering Information Sales Type ST72X774 (1) ST72E774J9D0 ST72T774J9B1 ST72774J9B1/xxx ST72774J7B1/xxx ST72774S7T1/xxx ST72T774S9T1 ST72774S9T1/xxx ST72X754 (1) ST72E754J9D0 ST72T754J9B1 ST72754J9B1/xxx ST72754J7B1/xxx ST72T754S9T1 ST72754S9T1 ST72754S7T1/xxx ST72X734 (2) ST72E734J6D0 ST72T734J6B1/xxx ST72734J6B1/xxx (1) 8 bit ±2 LSB A/D converter (2) 8 bit ±4 LSB A/D converter 142/144 RAM ROM/EPROM (bytes) ...
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... Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only. Mask Options: We have checked the ROM code verification file returned STMicroelectronics. It conforms exactly with the ROM code file orginally supplied. We therefore authorize STMicroelectronics to proceed with device manufacture. ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...