CY7C09379-6AC Cypress Semiconductor Corp, CY7C09379-6AC Datasheet
CY7C09379-6AC
Specifications of CY7C09379-6AC
Related parts for CY7C09379-6AC
CY7C09379-6AC Summary of contents
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... IDT709279 I/O Control Control Counter/ Address True Dual-Ported Register RAM Array Decode for x18 devices. 17 for x18 devices. 8 • 3901 North First Street CY7C09279/89 CY7C09379/89 32K/64K x16/ 0 0/1 8/9 I/O 8/9R I/O 8/9 15/16 Counter/ Address Register Decode • ...
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... Functional Description The CY7C09279/89 and CY7C09379/89 are high-speed syn- chronous CMOS 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, and data lines allow for minimal set- up and hold times ...
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... Data, Pipelined) Typical Operating Current I (mA) CC Typical Standby Current for I (mA) SB1 (Both Ports TTL Level) Typical Standby Current for I (mA) SB3 (Both Ports CMOS Level) Note: 8. This pin is NC for CY7C09379. Document #: 38-06040 Rev. *A 100-Pin TQFP (Top View CY7C09389 (64K x 18) ...
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... I/O –I/O for x16) of the memory array. For read operations both Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >1100V Latch-Up Current..................................................... >200 mA Operating Range Range Commercial [10] Industrial CY7C09279/89 CY7C09379/89 AND CE must be asserted MAX –I/O ). 8/9L 15/17L Ambient Temperature +70 C ...
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... Test Conditions T = 25° MHz 5.0V CC AND CE must be asserted to their active states ( CY7C09279/89 CY7C09379/89 -9 -12 Unit 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V 0.8 0.8 V –10 10 – 215 360 195 300 mA ...
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... Document #: 38-06040 Rev 250 TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) [12] 3.0V 10% GND Capacitance (pF) (b) Load Derating Curve CY7C09279/89 CY7C09379/ 893 OUTPUT 347 (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) ALL INPUT PULSES 90% 90% 10 Page ...
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... Test conditions used are Load 2. 14. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06040 Rev. *A CY7C09279/89 CY7C09379/89 [ Min. Max. Min. Max. Min. Max 100 6.5 7.5 12 6 6.5 7 CY7C09279/89 CY7C09379/89 -12 Min. Max. Unit 33 MHz 50 MHz Page [+] Feedback ...
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... Q n n+1 t OHZ [15, 16, 17, 18 CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09279/89 CY7C09379/ n+3 t CKHZ Q n OLZ n n+1 n+2 t OHZ ...
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... Document #: 38-06040 Rev CD2 HC CD2 SC CKHZ CKLZ [21, 22, 23, 24] NO MATCH t CD1 NO MATCH t CWDD VALID . for the left port, which is being written to. IH CY7C09279/89 CY7C09379/ CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not CWDD CCS Page [+] Feedback ...
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... During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06040 Rev. *A [18, 25, 26, 27 n+1 n CD2 CKHZ OPERATION [18, 25, 26, 27 n+1 n+2 n n+2 n+3 t CD2 OHZ WRITE . IH CY7C09279/89 CY7C09379/ n+3 n CD2 CKLZ Q n+3 WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Page [+] Feedback ...
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... DATA OUT OE Document #: 38-06040 Rev. *A [16, 18, 25, 26 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [16, 18, 25, 26 n+1 n+2 n n+2 n OHZ READ WRITE CY7C09279/89 CY7C09379/ n+3 n CD1 CD1 Q n CKLZ WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ DC READ Page [+] Feedback ...
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... Document #: 38-06040 Rev. *A [28 SAD t t SCN t CD2 n+1 COUNTER HOLD READ WITH COUNTER [28 n+1 n+2 READ WITH COUNTER . IH CY7C09279/89 CY7C09379/89 HAD HCN Q Q n+2 n+3 READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+3 READ COUNTER HOLD WITH COUNTER Page [+] Feedback ...
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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06040 Rev. *A [29, 30 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09279/89 CY7C09379/ n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH Page [+] Feedback ...
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... SD DATA DATA OUT COUNTER RESET Notes: 31 UB, and 32. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06040 Rev WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09279/89 CY7C09379 READ READ ADDRESS n Page [+] Feedback ...
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... CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09279/89 CY7C09379/89 Operation [36] Deselected [36] Deselected Write [34] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page [+] Feedback ...
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... Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09289-6AC 7.5 CY7C09289-7AC 9 CY7C09289-9AC CY7C09289-9AI 12 CY7C09289-12AC 32K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09379-6AC 7.5 CY7C09379-7AC 9 CY7C09379-9AC 12 CY7C09379-12AC 64K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09389-6AC 7.5 CY7C09389-7AC 9 CY7C09389-9AC CY7C09389-9AI 12 CY7C09389-12AC Document #: 38-06040 Rev ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C09279/89 CY7C09379/89 51-85048-B Page ...
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... Document Title: CY7C09279/89, CY7C09379/89 32K/64K X 16/18 Synchronous Dual Port Static RAM Document Number: 38-06040 Issue Orig. of REV. ECN NO. Date Change ** 110188 09/29/01 SZV *A 122290 12/27/02 RBI Document #: 38-06040 Rev. *A Description of Change Change from Spec number: 38-00664 to 38-06040 Power up requirements added to Maximum Ratings information ...