CY7C09379V-6AC Cypress Semiconductor Corp, CY7C09379V-6AC Datasheet

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CY7C09379V-6AC

Manufacturer Part Number
CY7C09379V-6AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C09379V-6AC

Density
576Kb
Access Time (max)
15ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
53MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
15b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
320mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
18b
Number Of Words
32K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C09379V-6AC
Manufacturer:
CYPRESS
Quantity:
174
Features
Notes
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *C
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O
4. I/O
5. A
True dual-ported memory cells that allow simultaneous access
of the same memory location
Six flow through/pipelined devices:
Three modes:
Pipelined output mode on both ports allows fast 100 MHz
operation
0.35 micron CMOS for optimum speed and power
High speed clock to data access: 6.5
Logic Block Diagram
16K x 16/18 organization (CY7C09269V/369V)
32K x 16/18 organization (CY7C09279V/379V)
64K x 16/18 organization (CY7C09289V/389V)
Flow through
Pipelined
Burst
R/ W
UB
CE
CE
LB
OE
FT /Pipe
I/O
I/O
A
CLK
ADS
CNTEN
CNTRST
0
0L
–A
8
0
–I/O
–I/O
L
8/9L
0L
L
0L
1L
L
–A
13
L
L
L
–I/O
for 16K; A
15
7
13/14/15L
–I/O
[5]
for x16 devices. I/O
L
L
for x16 devices; I/O
L
7/8L
[4]
[3]
15/17L
0
–A
14/15/16
14
for 32K; A
8/9
8/9
0
9
–I/O
–I/O
0/1
0
8
–A
0/1
17
1
0
1b
for x18 devices.
Counter/
Register
Address
Decode
15
for x18 devices.
b
0b 1a 0a
for 64K devices.
[1, 2]
a
, 7.5
[2]
198 Champion Court
, 9, 12 ns (max)
Control
I/O
True Dual-Ported
RAM Array
Synchronous Dual-Port Static RAM
3.3V low operating power:
Fully synchronous interface for easier operation
Burst counters increment addresses internally:
Dual chip enables easy depth expansion
Upper and lower byte controls for bus matching
Automatic power down
Commercial and industrial temperature ranges
Pb-Free 100-pin TQFP package available
Control
Active = 115 mA (typical)
Standby = 10 μA (typical)
Shorten cycle times
Minimize bus noise
Supported in flow through and pipelined modes
I/O
3.3V 16K/32K/64K x 16/18
San Jose
0a
,
a
1a
Counter/
Address
Register
CA 95134-1709
Decode
0b
CY7C09269V/79V/89V
CY7C09369V/79V/89V
b
1b
0/1
1
0
0/1
8/9
8/9
14/15/16
Revised March 25, 2009
I/O
A
8/9R
I/O
0R
–A
CNTRST
0R
408-943-2600
–I/O
FT /Pipe
CNTEN
13/14/15R
–I/O
[5]
ADS
15/17R
R/ W
CLK
CE
CE
UB
OE
LB
7/8R
[3]
[4]
0R
1R
R
R
R
R
R
R
R
R
R
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CY7C09379V-6AC Summary of contents

Page 1

... A –A for 32K; A –A for 64K devices Cypress Semiconductor Corporation Document #: 38-06056 Rev. *C 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM ■ 3.3V low operating power: ❐ Active = 115 mA (typical) Standby = 10 μA (typical) ❐ ■ Fully synchronous interface for easier operation ■ ...

Page 2

Pinouts 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [6] [7] A15L LBL 10 UBL 11 CE0L 12 CE1L 13 CNTRSTL 14 VCC 15 R/WL 16 OEL ...

Page 3

... Typical Standby Current for I (mA) SB1 (Both Ports TTL Level) Typical Standby Current for I (μA) SB3 (Both Ports CMOS Level) Notes 9. This pin is NC for CY7C09369V. 10. This pin is NC for CY7C09369V and CY7C09379V. Document #: 38-06056 Rev. *C Figure 2. 100-Pin TQFP (Top View ...

Page 4

Pin Definitions Left Port Right Port A –A A –A Address Inputs (A 0L 15L 0R 15R ADS ADS Address Strobe Input. Used as an address qualifier. This signal must be asserted LOW to access L R the part using ...

Page 5

Maximum Ratings [12] Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied.................................................. −55°C to +125°C Supply Voltage to Ground Potential .................−0.5V ...

Page 6

R1 = 590Ω OUTPUT 435Ω (a) Normal Load (Load 1) Figure 4. AC Test Loads (Applicable to -6 and -7 only 50Ω 50Ω 0 OUTPUT C (a) Load 1 ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description f f Flow Through MAX1 Max f f Pipelined MAX2 Max t Clock Cycle Time - Flow Through CYC1 t Clock Cycle Time - Pipelined CYC2 t Clock HIGH Time - Flow ...

Page 8

Switching Waveforms Figure 5. Read Cycle for Flow Through Output (FT/PIPE = V t CYC1 t CH1 CLK R ADDRESS t CD1 ...

Page 9

Switching Waveforms (continued) t CYC2 t t CH2 CL2 CLK ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2 0(B2 ...

Page 10

Switching Waveforms (continued) Figure 9. Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA ...

Page 11

Switching Waveforms (continued) Figure 11. Flow Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R ADDRESS DATA IN ...

Page 12

Switching Waveforms (continued) Figure 13. Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN t t SCN HCN DATA OUT Q x-1 READ ...

Page 13

Switching Waveforms (continued) Figure 15. Write with Address Counter Advance (Flow Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t ...

Page 14

Switching Waveforms (continued) Figure 16. Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST CNTRST t ...

Page 15

Read/Write and Enable Operation Inputs OE CLK Address Counter Control Operation Previous Address CLK ADS Address ...

Page 16

... Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09279V-6AC CY7C09279V-6AXC [2] 7.5 CY7C09279V-7AC CY7C09279V-7AXC 9 CY7C09279V-9AC CY7C09279V-9AI 12 CY7C09279V-12AC CY7C09279V-12AXC 64K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09289V-6AC CY7C09289V-6AXC [2] 7.5 CY7C09289V-7AC CY7C09289V-7AXC 9 CY7C09289V-9AC CY7C09289V-9AXC CY7C09289V-9AI CY7C09289V-9AXI 12 CY7C09289V-12AC CY7C09289V-12AXC Document #: 38-06056 Rev ...

Page 17

... CY7C09369V-7AC CY7C09369V-7AXC CY7C09369V-7AI 9 CY7C09369V-9AC CY7C09369V-9AXC CY7C09369V-9AI 12 CY7C09369V-12AC CY7C09369V-12AXC 32K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09379V-6AC CY7C09379V-6AXC [2] 7.5 CY7C09379V-7AC 9 CY7C09379V-9AC CY7C09379V-9AI 12 CY7C09379V-12AC CY7C09379V-12AXC CY7C09379V-12AXCT 64K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09389V-6AC ...

Page 18

Package Diagrams Figure 17. 100-Pin Thin Plastic Quad Flat Pack (TQFP), 51-85048 Document #: 38-06056 Rev. *C CY7C09269V/79V/89V CY7C09369V/79V/89V 51-85048 *C Page [+] Feedback [+] Feedback ...

Page 19

... Description of Change Change SZV Change from Spec number: 38-00668 to 38-06056 RBI Power up requirements added to Maximum Ratings Information PCX Added Pb-Free Part Ordering Information VKN/AESA Added CY7C09379V-12AXCT part. Updated 51-85048 to *C. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image ...

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