CY7C1061AV33-12ZC Cypress Semiconductor Corp, CY7C1061AV33-12ZC Datasheet
CY7C1061AV33-12ZC
Specifications of CY7C1061AV33-12ZC
Related parts for CY7C1061AV33-12ZC
CY7C1061AV33-12ZC Summary of contents
Page 1
... LOW), the outputs are disabled (OE HIGH), the 2 BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE The CY7C1061AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 60-ball fine-pitch ball grid array (FBGA) package. I/O – ...
Page 2
... DNU pins have to be left floating or tied to VSS to ensure proper application. Document #: 38-05256 Rev. *F Commercial Industrial Commercial/Industrial 60-ball FBGA (Top View BLE I BHE I I/O I I I/O I I/O I I/O DNU CY7C1061AV33 –10 –12 Unit 275 260 mA 275 260 Page ...
Page 3
... CC [ ponents of the test environment. ALL INPUT PULSES 90% 90% 10% 10% Fall time: > 1V/ns (c) to the data retention (V DD CY7C1061AV33 [3] ................................ –0. Ambient Temperature 3.3V ± 0.3V 0°C to +70°C –40°C to +85°C –10 –12 Min. Max. Min. Max. 2.4 2.4 0.4 ...
Page 4
... DD power are specified with a load capacitance ( Test Loads. Transition is measured ±200 mV from steady-state , t LZBE LOW (CE HIGH) and WE LOW. Chip enables must be active and WE and byte enables must 1 2 CY7C1061AV33 –10 –12 Min. Max. Min. Max ...
Page 5
... Address valid prior to or coincident with CE 1 Document #: 38-05256 Rev. *F DATA RETENTION MODE 3.0V V > CDR OHA ACE t DOE t LZOE t DBE t LZBE 50% . CE2 = transition LOW and CE transition HIGH. 2 CY7C1061AV33 3. DATA VALID t HZOE t HZCE t HZBE HIGH IMPEDANCE DATA VALID t PD 50% I ICC Page ...
Page 6
... BHE, BLE WE CE DATAI/O Notes: 16. Data I/O is high-impedance BHE and/or BLE = V 17 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state shorthand combination of both CE 1 Document #: 38-05256 Rev SCE PWE PWE t SCE . IH and CE combined active LOW. 2 CY7C1061AV33 Page ...
Page 7
... Switching Waveforms (continued) Write Cycle No. 3(WE Controlled, OE LOW) ADDRESS BHE, BLE DATA I/O Document #: 38-05256 Rev. *F [16,17,18 SCE PWE HZWE SD CY7C1061AV33 LZWE Page ...
Page 8
... Ordering Information Speed (ns) Ordering Code 10 CY7C1061AV33-10ZXC CY7C1061AV33-10BAC CY7C1061AV33-10ZI CY7C1061AV33-10ZXI CY7C1061AV33-10BAI 12 CY7C1061AV33-12ZC CY7C1061AV33-12ZXC CY7C1061AV33-12BAC CY7C1061AV33-12ZI CY7C1061AV33-12ZXI CY7C1061AV33-12BAI Contact local Cypress representative for availability of the these parts. Document #: 38-05256 Rev. *F I/O –I/O I/O –I High-Z High-Z Power-down X High-Z High-Z Power-down L Data Out Data Out ...
Page 9
... Package Diagrams Document #: 38-05256 Rev. *F 54-pin TSOP II (51-85160) CY7C1061AV33 51-85160-** Page ...
Page 10
... Cypress against all charges. BOTTOM VIEW A1 CORNER DUMMY BALL (0.3) X12 Ø0. Ø0. Ø0.30±0.05(48X 1.875 A 0.75 0.75 1.00 3.75 6.00 B 8.00±0.10 0.15(4X) CY7C1061AV33 DIMENSIONS IN MM PART # STANDARD PKG. BA60A LEAD FREE PKG. BK60A PKG WEIGHT: 0.30 gms 51-85162-*D Page ...
Page 11
... Document History Page Document Title: CY7C1061AV33 Static RAM Document Number: 38-05256 Issue REV. ECN NO. Date ** 113725 03/28/02 *A 117058 07/31/02 *B 117989 08/30/02 *C 120383 11/06/02 *D 124439 2/25/03 *E 492137 See ECN *F 508117 See ECN Document #: 38-05256 Rev. *F Orig. of Change Description of Change NSL New Data Sheet ...