ADMC300BST Analog Devices Inc, ADMC300BST Datasheet
ADMC300BST
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ADMC300BST Summary of contents
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ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS PROGRAM SEQUENCER DAG 1 DAG 2 PROGRAM MEMORY ADDRESS BUS DATA MEMORY ADDRESS BUS PROGRAM MEMORY DATA BUS DATA MEMORY DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER High Performance DSP-Based FUNCTIONAL BLOCK DIAGRAM ...
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ADMC300–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Digital Supply Voltage DD AV Analog Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter V Hi-Level Input Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output Voltage OH V Lo-Level ...
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ANALOG-TO-DIGITAL CONVERTER Parameter 1 Signal-to-Noise Ratio (SNR) 1 Total Harmonic Distortion (THD) 2 Common-Mode Rejection Ratio (CMRR) 3 Channel-Channel Crosstalk Gain Error Gain 4 V Analog Input Range IN V Analog Input Voltage (Differential) DIFF Offset Voltage ...
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ADMC300–SPECIFICATIONS ENCODER INTERFACE UNIT Parameter f Maximum Encoder Pulse Rate ENC, MAX NOTES 1 Assumes perfect quadrature encoder signals. Specifications subject to change without notice. AUXILIARY PWM OUTPUTS Parameter Resolution f Switching Frequency AUXPWM Specifications subject to change without notice. ...
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... Input Voltage . . . . . . . . . . . . . . . . . . . . –0 Output Voltage Swing . . . . . . . . . . . . . –0 Operating Temperature Range (Ambient – 40°C to +85°C Temperature Model Range ADMC300BST –40°C to +85°C ADMC300-ADVEVALKIT ADMC300-PB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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ADMC300 Pin Pin Pin Pin Pin No. Type Name No. Type 1 GND GND DR0 DT0 23 4 I/O RFS0 I/O TFS0 26 6 I/O SCLK0 7 SUP ...
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Page 1) GENERAL DESCRIPTION The ADMC300 is a single-chip DSP-based controller, suitable for high performance control of ac induction motors, permanent magnet synchronous motors and brushless dc motors. The ADMC300 integrates a 25 MIPS, fixed-point DSP core with ...
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ADMC300 DATA DATA ADDRESS ADDRESS GENERATOR GENERATOR #1 #2 INPUT REGS INPUT REGS ALU MAC OUTPUT REGS OUTPUT REGS DSP CORE ARCHITECTURE OVERVIEW Figure overall block diagram of the DSP core of the ADMC300, which is based ...
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Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four address pointers (I registers). Whenever the pointer is used to access data (indirect addressing ...
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ADMC300 PIN FUNCTION DESCRIPTION The ADMC300 is available in an 80-lead TQFP package. Table I contains the pin descriptions. Table I. Pin List Pin # Group of Input/ Name Pins Output Function RESET 1 I Processor Reset Input. SPORT0 5 ...
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Table IV. ROM Utilities Utility Address Function PER_RST 0x07E4 Peripheral Reset. UMASK 0x0E21 Limits Unsigned Value to Given Range. PUT_VECTOR 0x0E28 Facilitates User Setup of Vector Table. SMASK 0x0E35 Limits Signed Value to Given Range. ADMC_COS 0x0E55 Cosine Function. ADMC_SIN ...
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ADMC300 program and data memory RAM can be loaded from the SROM PROM. After the boot load is complete, program execution begins at address 0x0060. This is where the first instruction of the user code should be placed. ...
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The sigma-delta converter consists of two stages, a modulator and a sinc filter, that combine to produce a 16-bit conversion. For ...
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ADMC300 The corresponding configuration for single-ended operation is shown in Figure 7, where the inverting input is now tied directly to the reference voltage level. The noninverting input antialiasing filter with a cutoff at 34 kHz is ...
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ADC sample period is effectively subdivided into 128 equal time slices. The value written to the ADCSYNC register is the number of such time slices before the PWMSYNC pulse that the CONVST ...
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ADMC300 ADC Group Delay The digital filters of the ADCs carry out two important func- tions. First, they remove the out-of-band quantization noise, which has been suitably shaped by the noise-shaping circuits of the input modulator stages. The digital filters ...
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It is recommended that prior to use, a full reset be performed. ADC Registers The composition of all the data registers associated with the ...
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ADMC300 The PWM controller is driven by a clock at the same frequency as the DSP instruction rate, CLKOUT, and is capable of gener- ating two interrupts to the DSP core. One interrupt is generated on the occurrence of a ...
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In single update mode, a single PWMSYNC pulse is produced in each PWM period. The rising edge of this signal marks the start of a new PWM cycle and is used to latch new values from the PWM configuration registers ...
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ADMC300 T PWMTM – PWMCHA – PWMDT = PWMTM S The minimum permissible T and sponding duty cycle similar fashion, the maximum value corresponding ...
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In each half cycle of the PWM, the timing unit checks the on- time of each of the six PWM signals. If any of the times is found to be less than the value specified by the PWMPD regis- ter, ...
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ADMC300 Typical PWM output signals with high frequency chopping enabled on both high-side and low-side signals are shown in Figure 15. Chopping of the high side PWM outputs (AH, BH and CH) is enabled by setting Bit 8 of the ...
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EIUMAXCNT. There is also a single north marker mode avail- able in which the encoder quadrature counter is reset only on the first zero pulse. Both modes are enabled by dedicated con- trol bits in the EIU control register, EIUCTRL. ...
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ADMC300 Encoder Counter Reset The ZERO bit (Bit 1) of the EIUCTRL register determines if the encoder zero marker is used to reset the up/down counter of the encoder interface. When Bit 1 of the EIUCTRL register is set, the ...
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EIA EIB QUADRATURE SIGNAL EIUCNT VELOCITY EVENTS ENCODER EVENT TIMER VALUE EIUCNT READ Encoder Event Timer The Encoder Event Timer block forms an integral part of the EIU of the ADMC300. The EET accurately times the duration between encoder events. ...
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ADMC300 EIU/EET Registers The EIU and EET registers are summarized at the end of the data sheet. PROGRAMMABLE INPUT/OUTPUT The ADMC300 has 12 programmable digital input/output pins called PIO0 to PIO11. Each pin may be individually configured as either an ...
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PIO lines will cause a PWM trip. Therefore, prior to using the PWM unit of the ADMC300 imperative that the PIO state be correctly configured for the particular application. PIO Registers The configuration ...
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ADMC300 digital outputs using the PIODIR register. In this mode, writing suitable patterns to the PIODATA register will trigger the corresponding event capture on the ETU channels. ETU Interrupt Generation The completion of the event capture sequence can be defined ...
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Interrupt Configuration The IFC and ICNTL registers of the DSP core control and configure the interrupt controller of the DSP core. The IFC register is a 16-bit register that may be used to force and/or clear any of the eight ...
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ADMC300 SPORT1. Two control bits in the MODECTRL register control the state of the SPORT1 pins by manipulating internal multi- plexers in the ADMC300. The configuration of SPORT1 is illustrated in Figure 19. Bit 4 of the MODECTRL register (DR1SEL) ...
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Address Name 0x2000–0x2007 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXTIM0 0x2011 AUXTIM1 0x2012–0x2014 0x2015 MODECTRL 0x2016 SYSSTAT 0x2017 0x2018 WDTIMER 0x2019–0x201B 0x201C PICVECTOR 0x201D PICMASK 0x201E-0x201F 0x2020 EIUCNT 0x2021 ...
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ADMC300 Table VIII. Peripheral Register Map of ADMC300 (Continued) Address Name 0x2051 ETUB0 0x2052 ETUAA0 0x2053 ETUA1 0x2054 ETUB1 0x2055 ETUAA1 0x2056 ETUTIME 0x2057–0x205B 0x205C ETUCONFIG 0x205D ETUDIVIDE 0x205E ETUSTAT 0x205F ETUCTRL 0x2060 PWMSYNCWT 0x2061 PWMSWT 0x2062-0x20FF Address Name 0x3FFF ...
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NORMAL FILTER MODE 1 = RESET 0 = NORMAL MODULATOR MODE 1 = RESET RESERVED (SET TO 1) REFERENCE 0 = POWER-ON POWER-DOWN 1 = POWER-DOWN BANK B POWER-DOWN ...
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ADMC300 Default bit values are shown value is ...
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LOW-SIDE CHOPPING 1 = ENABLE 0 = DISABLE HIGH-SIDE CHOPPING 15 14 AH/AL CROSSOVER 1 = ENABLE BH/BL CROSSOVER 0 = DISABLE CH/CL CROSSOVER Default bit values are ...
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ADMC300 RECEIVED FIRST ZERO MARKER 0 = NOT RECEIVED EIZP STATE EIB STATE EIA STATE 15 ...
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ADMC300 ...
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SINGLE-SHOT ETU1 MODE 1 = FREE-RUNNING 0 = NEXT EVENT ...
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ADMC300 PERIPHERAL (OR IRQ2) RESERVED (SET DISABLE (MASK) SPORT0 TRANSMIT 1 = ENABLE SPORT0 RECEIVE SOFTWARE PIO3 0 = DISABLE PIO2 (MASK ENABLE PIO1 PIO0 ...
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DOUBLE UPDATE 0 = SINGLE UPDATE SECOND HALF CYCLE 0 = FIRST HALF CYCLE DISABLED SPORT0 ENABLE 1 = ENABLED 0 = DISABLED SPORT1 ENABLE 1 ...
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ADMC300 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead TQFP (ST-80) 0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.063 (1.60) MAX 0.549 (13.95) 0.486 (12.35) TYP 0.030 (0.75) 0.020 (0.50 SEATING PLANE TOP VIEW (PINS DOWN) 0.004 80 ...