CY62148VLL-70SI

Manufacturer Part NumberCY62148VLL-70SI
ManufacturerCypress Semiconductor Corp
CY62148VLL-70SI datasheets

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Specifications of CY62148VLL-70SI

Density4MbAccess Time (max)70ns
Package TypeSOICOperating Temp Range-40C to 85C
Supply Current15mAOperating Supply Voltage (min)2.7V
Operating Supply Voltage (max)3.6VOperating Temperature ClassificationIndustrial
MountingSurface MountPin Count32
Word Size8bLead Free Status / Rohs StatusNot Compliant
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Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low-Z
LZOE
t
OE HIGH to High-Z
HZOE
t
CE LOW to Low-Z
LZCE
t
CE HIGH to High-Z
HZCE
t
CE LOW to Power-up
PU
t
CE HIGH to Power-down
PD
[9, 10]
Write Cycle
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Set-up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-up to Write Start
SA
t
WE Pulse Width
PWE
t
Data Set-up to Write End
SD
t
Data Hold from Write End
HD
t
WE LOW to High-Z
HZWE
t
WE HIGH to Low-Z
LZWE
Switching Waveforms
[11, 12]
Read Cycle No. 1
ADDRESS
DATA OUT
PREVIOUS DATA VALID
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
specified I
/I
and 30 pF load capacitance.
OL
OH
7.
At any given temperature and voltage condition, t
8.
t
, t
, and t
are specified with C
HZOE
HZCE
HZWE
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
Document #: 38-05070 Rev. *A
[6]
Description
[7]
[8]
[7]
[7, 8]
[7, 8]
[7]
t
RC
t
AA
t
OHA
is less than t
, t
is less than t
HZCE
LZCE
HZOE
LZOE
= 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
L
and t
HZWE
CY62148V MoBL
CY62148V-70
Min.
Max.
Unit
70
ns
70
ns
10
ns
70
ns
35
ns
5
ns
25
ns
10
ns
25
ns
0
ns
70
ns
70
ns
60
ns
60
ns
0
ns
0
ns
50
ns
30
ns
0
ns
25
ns
10
ns
DATA VALID
, and output loading of the
CC(typ.)
, and t
is less than t
for any given device.
HZWE
LZWE
.
SD
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