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CY62148VLL-70SI
CY62148VLL-70SI | |
|---|---|
| Manufacturer Part Number | CY62148VLL-70SI |
| Manufacturer | Cypress Semiconductor Corp |
| CY62148VLL-70SI datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
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Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of CY62148VLL-70SI | |||
|---|---|---|---|
| Density | 4Mb | Access Time (max) | 70ns |
| Package Type | SOIC | Operating Temp Range | -40C to 85C |
| Supply Current | 15mA | Operating Supply Voltage (min) | 2.7V |
| Operating Supply Voltage (max) | 3.6V | Operating Temperature Classification | Industrial |
| Mounting | Surface Mount | Pin Count | 32 |
| Word Size | 8b | Lead Free Status / Rohs Status | Not Compliant |
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Switching Waveforms
(continued)
[12, 13]
Read Cycle No. 2
CE
t
ACE
OE
t
LZOE
HIGH IMPEDANCE
DATA OUT
t
LZCE
t
PU
V
CC
SUPPLY
CURRENT
[9, 14, 15]
Write Cycle No. 1 (WE Controlled)
ADDRESS
CE
t
SA
WE
OE
16
DATA I/O
NOTE
t
HZOE
[9, 14, 15]
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
WE
DATA I/O
Notes:
11. Device is continuously selected. OE, CE = V
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = V
.
IH
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05070 Rev. *A
t
RC
t
DOE
DATA VALID
50%
t
WC
t
AW
t
PWE
t
SD
DATA
VALID
IN
t
WC
t
SCE
t
SA
t
AW
t
SD
DATA
VALID
IN
.
IL
CY62148V MoBL
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
I
CC
50%
I
SB
t
HA
t
HD
t
HA
t
HD
Page 5 of 9
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