CY62167DV30LL-70ZI Cypress Semiconductor Corp, CY62167DV30LL-70ZI Datasheet

CY62167DV30LL-70ZI

Manufacturer Part Number
CY62167DV30LL-70ZI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62167DV30LL-70ZI

Density
16Mb
Access Time (max)
70ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3V
Address Bus
20b
Package Type
TSOP-I
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
25mA
Operating Supply Voltage (min)
2.2V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Word Size
16b
Number Of Words
1M
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62167DV30LL-70ZI
Manufacturer:
CYPRESS
Quantity:
1 302
Cypress Semiconductor Corporation
Document #: 38-05328 Rev. *F
Features
Functional Description
The CY62167DV30 is a high-performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• Very high speed: 45 ns
• Wide voltage range: 2.20V – 3.60V
• Ultra-low active power
• Ultra-low standby power
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball BGA and 48-pin TSOPI
Logic Block Diagram
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 18.5 mA @ f = f
features
speed)
A
A
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
1
0
[1]
Power-down
Circuit
DATA IN DRIVERS
COLUMN DECODER
1
, CE
RAM Array
1M × 16
2
, and OE
3901 North First Street
max
(45 ns
®
) in
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE
HIGH). The input/output pins (I/O
in a high-impedance state when: deselected (CE
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a Write operation (CE
LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
through I/O
address pins (A
LOW, then data from I/O pins (I/O
the location specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enables (CE
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
High Enable (BHE) is LOW, then data from memory will appear
on I/O
sheet for a complete description of Read and Write modes.
BHE
BLE
16-Mbit (1M x 16) Static RAM
1
LOW and CE
8
to I/O
7
San Jose
1
), is written into the location specified on the
15
LOW and CE
1
. See the truth table at the back of this data
I/O0 – I/O7
I/O8 – I/O15
0
HIGH or CE
through A
2
HIGH) and Write Enable (WE) input LOW.
BHE
WE
OE
BLE
,
CA 95134
19
2
2
CE
CE
HIGH) and Output Enable (OE)
). If Byte High Enable (BHE) is
LOW or both BHE and BLE are
1
2
8
1
0
Revised December 20, 2004
through I/O
LOW, CE
through I/O
CE
CE
CY62167DV30
1
2
2
0
15
through A
0
HIGH and WE
15
) is written into
1
to I/O
HIGH or CE
) are placed
408-943-2600
MoBL
7
. If Byte
19
).
®
2
0

Related parts for CY62167DV30LL-70ZI

CY62167DV30LL-70ZI Summary of contents

Page 1

... Power-down Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05328 Rev. *F 16-Mbit (1M x 16) Static RAM also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling ...

Page 2

... Typ. 2.20 3.0 CY62167DV30L CY62167DV30LL Notes pins are not connected on the die. 3. DNU pins have to be left floating. 4. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device × 16 SRAM. The 48-TSOPI package can also be used × 8 SRAM by tying the BYTE signal LOW. For 2M × ...

Page 3

... Full Device AC operation requires linear V CC Document #: 38-05328 Rev. *F Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range + 0.3V Device CC CY62167DV30L + 0.3V CC CY62167DV30LL + 0.3V CC CY62167DV30-45 [6] Min. Typ. Max. Min. Typ 2.0 CC 2.20V ...

Page 4

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT Thermal Resistance Parameter Description Θ Thermal Resistance JA [10] (Junction to Ambient) Θ Thermal Resistance JC [10] (Junction to Case) AC Test Loads and Waveforms R1 V ...

Page 5

Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW and CE ACE LOW to ...

Page 6

Switching Waveforms Read Cycle 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [20, 21] Read Cycle 2 (OE Controlled) ADDRESS ACE BHE/BLE t LZBE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 7

Switching Waveforms (continued) [18, 22, 23, 24] Write Cycle 1 (WE Controlled) ADDRESS BHE/BLE OE DATA I/O See Note 23 t HZOE Notes: 21. Address valid prior to or coincident with CE , ...

Page 8

Switching Waveforms (continued) Write Cycle 2 ( Controlled ADDRESS BHE/BLE OE DATA I/O See Note 23 t HZOE Write Cycle 3 (WE Controlled, OE LOW) ADDRESS ...

Page 9

Switching Waveforms (continued) Write Cycle 4 (BHE/BLE Controlled, OE LOW) ADDRESS BHE/BLE DATA I/O See Note 23 Truth Table BHE ...

Page 10

... Ordering Information Speed (ns) Ordering Code 45 CY62167DV30L-45ZI CY62167DV30LL-45ZI CY62167DV30LL-45ZXI 55 CY62167DV30L-55BVI CY62167DV30LL-55BVI CY62167DV30LL-55BVXI CY62167DV30L-55ZI CY62167DV30LL-55ZI CY62167DV30LL-55ZXI 70 CY62167DV30L-70BVI CY62167DV30LL-70BVI CY62167DV30LL-70BVXI CY62167DV30L-70ZI CY62167DV30LL-70ZI CY62167DV30LL-70ZXI Package Diagrams TOP VIEW A1 CORNER 8.00±0.10 SEATING PLANE C Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. ...

Page 11

... Document #: 38-05328 Rev. *F © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 12

Document History Page Document Title:CY62167DV30 MoBL Document Number: 38-05328 REV. ECN NO. Issue Date ** 118408 09/30/02 *A 123692 02/11/03 *B 126555 04/25/03 *C 127841 09/10/03 *D 205701 *E 238050 See ECN *F 304054 See ECN Document #: 38-05328 Rev. ...

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