CY7C199-12VI Cypress Semiconductor Corp, CY7C199-12VI Datasheet

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CY7C199-12VI

Manufacturer Part Number
CY7C199-12VI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C199-12VI

Density
256Kb
Access Time (max)
12ns
Operating Supply Voltage (typ)
5V
Package Type
SOJ
Operating Temp Range
-40C to 85C
Supply Current
160mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Word Size
8b
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C199-12VI
Manufacturer:
CYPRESS
Quantity:
455
Part Number:
CY7C199-12VI
Quantity:
200
Part Number:
CY7C199-12VIT
Quantity:
200
Features
Functional Description
The CY7C199 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
Selection Guide
Cypress Semiconductor Corporation
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum CMOS
Standby Current (mA)
Shaded area contains preliminary information.
CE
WE
• High speed
• Fast t
• CMOS for optimum speed/power
• Low active power
• Low standby power
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
OE
Logic Block Diagram
— 10 ns
— 467 mW (max, 12 ns “L” version)
— 0.275 mW (max, “L” version)
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
DOE
INPUT BUFFER
1024 x 32 x 8
DECODER
COLUMN
ARRAY
L
L
7C199-8
120
0.5
8
POWER
DOWN
7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45
0.05
110
0.5
10
90
3901 North First Street
C199–1
0.05
160
12
90
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power consump-
tion by 81% when deselected. The CY7C199 is in the standard
300-mil-wide DIP, SOJ, and LCC packages.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
through I/O
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
0
1
2
3
4
5
6
7
0.05
155
15
90
10
GND
V
WE
A
A
I/O
I/O
I/O
OE
A
A
A
A
A
A
A
A
A
CC
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
10
11
5
6
7
8
9
1
2
3
4
5
6
8
9
0
1
2
7
DIP / SOJ / SOIC
7
San Jose
) is written into the memory location addressed by
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
22
23
24
25
26
4
5
6
7
27
28
1
2
3
0.05
150
20
90
10
Pin Configurations
28
27
26
25
24
23
22
21
20
19
18
17
16
15
February 1988 – Revised April 22, 1998
32K x 8 Static RAM
I/O
V
WE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
A
CC
3
2
1
0
4
3
7
6
5
4
C199–2
(not to scale)
0.05
Top View
150
CA 95134
25
80
10
TSOP I
I/O
I/O
A
A
A
A
A
A
A
10
11
12
13
14
8
9
0
1
4
5
6
7
8
9
10
11
12
1314151617
Top View
3 2 1
0.05
140
35
70
10
LCC
CY7C199
fax id: 1030
0
28
408-943-2600
27
through A
26
25
24
23
22
21
20
19
18
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
CE
A
A
A
A
A
I/O
I/O
4
3
2
1
0
C199–3
140
7
6
45
10
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
C199–4
0
14
13
12
7
6
5
4
3
2
1
0
14
).
0

Related parts for CY7C199-12VI

CY7C199-12VI Summary of contents

Page 1

... LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consump- tion by 81% when deselected. The CY7C199 is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW write enable signal (WE) controls the writ- ing/reading operation of the memory ...

Page 2

... L = 1/t RC Mil , CE > Com’ MAX , Com’l 0.5 CC – 0. 0.05 – 0.3V CC Mil < 0.3V CY7C199 [2] Ambient Temperature +70 C – +85 C – +125 C 7C199-10 7C199-12 7C199-15 Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.2 V 2 +0.3V +0.3V – ...

Page 3

... RC Mil 170 , CE > Com’ MAX , Com’ – 0. 0.05 – 0. Mil 15 Test Conditions MHz 5. CY7C199 7C199-35 7C199-45 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0.4 V 2 +0.3V +0.3V +0.3V 0.8 -0.5 0.8 -0.5 0.8 +5 –5 +5 – –5 +5 – ...

Page 4

... Over the Operating Range (L version only) Conditions Com’ 2.0V > V – 0.3V, CC Com’ > V – 0. < 0.3V IN DATA RETENTION MODE 3.0V V > CDR 4 CY7C199 ALL INPUT PULSES 3.0V 90% 90% 10% GND t r [6] Min. Max C199–6 Unit C199–7 ...

Page 5

... The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t [3, 7] 7C199-8 7C199-10 Min. Max. Min. Max 4 and 30-pF load capacitance less than less than t , and t HZCE LZCE HZOE LZOE HZWE and t . HZWE SD 5 CY7C199 7C199-12 7C199-15 Min. Max. Min. Max. Unit ...

Page 6

... LZWE Switching Waveforms [12, 13] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID Notes: 12. Device is continuously selected HIGH for read cycle. [3,7] (continued) 7C199-20 7C199-25 Min. Max. Min. Max OHA . 6 CY7C199 7C199-35 7C199-45 Min. Max. Min. Max DATA VALID Unit ...

Page 7

... Data I/O is high impedance 16 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state ACE t DOE t LZOE 50 PWE t SD DATA SCE DATA 7 CY7C199 t HZOE t HZCE IMPEDANCE DATA VALID VALID VALID IN HIGH ICC ISB C199–9 C199–10 C199–11 ...

Page 8

... V =5. 0.0 –55 25 125 AMBIENT TEMPERATURE ( C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 V =5.0V CC 0.8 0.6 –55 25 125 AMBIENT TEMPERATURE ( C) 8 CY7C199 LZWE C199–12 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. = 0.0 1.0 2.0 3.0 4.0 ...

Page 9

... CY7C199-10ZC CY7C199L-10VC CY7C199L-10ZC CY7C199-10VI CY7C199-10ZI CY7C199L-10VI CY7C199L-10ZI 12 CY7C199-12PC CY7C199-12VC CY7C199-12ZC CY7C199L-12PC CY7C199L-12VC CY7C199L-12ZC CY7C199-12VI CY7C199-12ZI CY7C199L-12VI CY7C199L-12ZI Shaded area contains preliminary information. Contact your Cypress sales representative for availability (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 V =4.5V 10 ...

Page 10

... CY7C199-20PC CY7C199-20VC CY7C199-20ZC CY7C199L-20PC CY7C199L-20VC CY7C199L-20ZC CY7C199-20VI CY7C199-20ZI CY7C199-20DMB CY7C199-20LMB CY7C199L-20DMB CY7C199L-20LMB 25 CY7C199-25PC CY7C199-25SC CY7C199-25VC CY7C199-25ZC CY7C199L-25ZI CY7C199-25DMB CY7C199-25LMB 35 CY7C199-35PC CY7C199-35SC CY7C199-35VC CY7C199-35ZC CY7C199-35DMB CY7C199-35LMB 45 CY7C199-45DMB CY7C199-45LMB Shaded area contains preliminary information. Contact your Cypress sales representative for availability Package Type ...

Page 11

... CerDIP D22 MIL–STD–1835 D–15 Config.A Switching Characteristics Parameter Subgroups READ CYCLE 10 10 10, 11 OHA 10, 11 ACE 10, 11 DOE WRITE CYCLE 10, 11 PWE 10 10 Document #: 38–00239–E 28-Pin Rectangular Leadless Chip Carrier L54 MIL–STD–1835 C–11A 11 CY7C199 ...

Page 12

... Package Diagrams (continued) 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Molded SOIC S21 12 CY7C199 ...

Page 13

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOJ V21 28-Lead Thin Small Outline Package Z28 CY7C199 ...

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