JS28F128P30T85 Micron Technology Inc, JS28F128P30T85 Datasheet
JS28F128P30T85
Specifications of JS28F128P30T85
Related parts for JS28F128P30T85
JS28F128P30T85 Summary of contents
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... Individual zero-latency block locking — Individual block lock-down Software — 20 μs (Typ) program suspend — 20 μs (Typ) erase suspend — Numonyx™ Flash Data Integrator optimized — Basic Command Set and Extended Command Set compatible — Common Flash Interface capable Density and Packaging — ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. ...
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P30 Contents 1.0 Functional Description ............................................................................................... 5 1.1 Introduction ....................................................................................................... 5 1.2 Overview ........................................................................................................... 5 1.3 Virtual Chip Enable Description.............................................................................. 6 1.4 Memory Maps ..................................................................................................... 6 2.0 Package Information ................................................................................................. 9 2.1 56-Lead TSOP..................................................................................................... 9 2.2 64-Ball Easy BGA Package ...
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Lock-Down Block ....................................................................................36 10.1.4 Block Lock Status ...................................................................................37 10.1.5 Block Locking During Suspend ..................................................................37 10.2 Selectable One-Time Programmable Blocks ...........................................................38 11.0 Registers .................................................................................................................39 11.1 Read Status Register..........................................................................................39 11.1.1 Clear Status Register ..............................................................................40 11.2 Read Configuration Register ................................................................................40 11.2.1 Read ...
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... Numonyx™ StrataFlash densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, high- speed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices ...
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... The P30 protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable (OTP). ...
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P30 1.4 Memory Maps Table 3 through multiple 8-Mbit Programming Regions (see page 29). Table 3: Discrete Top Parameter Memory Maps (all packages) Size Blk (KB 3FC000 - 3FFFFF 32 63 3F0000 - 3F3FFF 128 62 3E0000 - ...
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... Block size is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K- Words where a Word is the size of the flash output bus (16 bits). Note: The Dual- Die P30 memory maps are the same for both parameter options because the devices employ virtual chip enable (Refer to the placement of bottom parameter die ...
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... Bottom Parameter Die Note: Refer to the appropriate 256-Mbit Memory Map ( is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-Words where a Word is the size of the flash output bus (16 bits). August 2008 Order Number: 306666-12 512-Mbit Flash (2x256-Mbit w/ 1CE) Size Blk ...
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Package Information 2.1 56-Lead TSOP Figure 1: TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 6: TSOP Package Dimensions (Sheet Product Information Symbol Package Height A Standoff ...
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... If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. 4. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://developer.Numonyx.com/design/flash/packtech. 2.2 64-Ball Easy BGA Package ...
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... Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Notes: 1. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://developer.Numonyx.com/design/flash/packtech. Datasheet 12 Millimeters Symbol Min Nom Max ...
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P30 2.3 QUAD+ SCSP Packages Figure 3: 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index Mark Top View - Ball Down ...
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Figure 4: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm Index Mark Top View - Ball Down A2 Note: Dimensions A1, A2, ...
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P30 Figure 5: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm Index Mark Top View - Ball Down A2 Dimensions Package ...
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... Please refer to the latest specification update for synchronous read operation with the TSOP package. The synchronous read input signals (i.e. ADV# and CLK) should be tied off to support asynchronous reads. See Datasheet 16 Intel StrataFlash® Embedded Memory (P30) 56-Lead TSOP Pinout Top View Section 4.0, “ ...
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P30 Figure 7: 64-Ball Easy BGA Ballout (64/128/256/512-Mbit VPP B A2 VSS A9 CE A10 A12 A11 RST# E DQ8 DQ1 DQ9 DQ3 F RFU DQ0 ...
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Figure 8: 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin A18 C A5 RFU D A3 A17 DQ8 H RFU DQ0 J RFU F1-OE# K ...
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... PPH cycles. VPP can be connected for a cumulative total not to exceed 80 hours. Extended use of this pin may reduce block cycling capability. Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when V ...
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... FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and F1-CE# Input WAIT outputs are placed in high-Z state ...
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... P30 Table 9: QUAD+ SCSP Signal Descriptions (Sheet Symbol Type Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when V CC VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. ...
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... Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. 5.2 ...
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... As with any automated device important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory the system boot device CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data ...
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... The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; ...
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P30 Table 11: Command Codes and Definitions (Sheet Mode Code Device Mode 0x20 Block Erase Setup Erase 0xD0 Block Erase Confirm Program or Erase 0xB0 Suspend Suspend 0xD0 Suspend Resume 0x60 Lock Block Setup 0x01 Lock Block ...
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Table 12: Command Bus Cycles Mode Command Read Array Read Device Identifier Read Read CFI Read Status Register Clear Status Register Word Program (3) Program Buffered Program Buffered Enhanced Factory (4) Program (BEFP) Erase Block Erase Program/Erase Suspend Suspend Program/Erase ...
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... AVQV In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay ...
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... The 512-Mbit devices do not have a Device ID associated with them. Each die within the stack can be identified by either of the 256-Mbit Device ID codes depending on its parameter option. 7.4 Read CFI The Read CFI command instructs the device to output Common Flash Interface (CFI) data when read. See Read CFI command. CFI information and address offsets within the CFI database. ...
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... System designs must use these definitions when partitioning their code and data for the P30 device. • Code: Execution code ran out of the flash device on a continuous basis in the system. • Data: Information periodically programmed into the flash device and read back (e ...
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... The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. ...
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... Status Register should be cleared using the Clear Status Register command. 8.4 Buffered Enhanced Factory Programming Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash programming. The enhanced programming algorithm used in BEFP eliminates traditional programming elements that drive up overhead in device programmer systems ...
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... During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. ...
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P30 only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[ and the device is ready for the next buffer fill. Note: Any ...
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Program Protection When absolute hardware write protection is provided for all device blocks below V PP level error. Block lock registers are not affected by the voltage level ...
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... P30 9.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. ...
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Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. During an erase suspend, deasserting CE# places the device in standby, reducing active current. V while in ...
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... The following sections describe each security mode in detail. 10.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. ...
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Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 12.0, “Power and Reset Specifications” on page the addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 ...
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P30 If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. ...
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Registers When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will ...
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P30 Table 18: Status Register Description (Sheet Status Register (SR) 2 Program Suspend Status (PSS) 1 Block-Locked Status (BLS) 0 BEFP Status (BWS) Note: Always clear the Status Register prior to resuming erase operations. It avoids Status ...
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Table 19: Read Configuration Register Description (Sheet Latency Count (LC[2:0]) 13:11 Wait Polarity (WP) 10 Data Hold (DH Wait Delay (WD) Burst Sequence (BS) 7 Clock Edge (CE) 6 5:4 Reserved (R) Burst Wrap (BW) ...
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P30 Figure 13: First-Access Latency Count CLK [C] Address [A] Valid Address ADV# [V] Code 0 (Reserved) DQ [D/Q] Valid 15-0 Output Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 Code 4 ...
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Figure 14: Example Latency Count Setting using Code 3 CLK CE# ADV# A[MAX:0] D[15:0] 11.2.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V WAIT. When WP is set, WAIT is asserted high (default). When WP ...
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... When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see time and the flash memory’s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for ...
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Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. lengths, as well as the effect of the Burst Wrap (BW) setting. Table 22: Burst Sequence Word Ordering Start Burst Addr. Wrap 4-Word ...
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... Burst Length The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length ...
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Each OTP Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated OTP Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when ...
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P30 11.3.2 Programming the OTP Registers To program any of the OTP Registers, first issue the Program OTP Register command at the parameter’s base address plus the offset to the desired OTP Register (see 6.0, “Command Set” on page same ...
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... Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...
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... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Numonyx Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground ...
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Maximum Ratings and Operating Conditions 13.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 24: Maximum Ratings Parameter Temperature under bias Storage temperature Voltage on ...
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P30 14.0 Electrical Specifications 14.1 DC Current Characteristics Table 26: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], LO WAIT Current 64-Mbit 128-Mbit Standby, CCS CC I ...
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Table 26: DC Current Characteristics (Sheet Sym Parameter I V Erase Current PPE PP Notes: 1. All currents are RMS unless noted. Typical values at typical the average current measured over any 5 ...
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P30 15.0 AC Characteristics 15.1 AC Test Conditions Figure 18: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ and fall times (10% to 90%) < 5 ns. Worst ...
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Capacitance Table 29: Capacitance Parameter Signals Address, Data, CE#, WE#, OE#, Input Capacitance RST#, CLK, ADV#, WP# Output Capacitance Data, WAIT Notes: 1. Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values ...
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P30 Table 30: AC Read Specifications for 64/128- Mbit Densities (Sheet Num Symbol R108 t Page address access APA R111 t RST# high to ADV# high phvh Clock Specifications R200 f CLK frequency CLK R201 t CLK ...
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Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet Num Symbol R3 t CE# low to output valid ELQV R4 t OE# low to output valid GLQV R5 t RST# high to output valid PHQV R6 t ...
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P30 Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet Num Symbol R301 t Address setup to CLK AVCH/L R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 t ...
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Figure 21: Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 22: Asynchronous Single-Word Read ...
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... WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. August 2008 ...
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Figure 25: Continuous Burst Read, Showing An Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Notes: 1. WAIT ...
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P30 15.4 AC Write Specifications Table 33: AC Write Specifications Num Symbol W1 t RST# high recovery to WE# low PHWL W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH W4 t Data ...
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Figure 27: Write-to-Write Timing W5 Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Figure 28: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data [D/Q] ...
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P30 Figure 29: Write-to-Asynchronous Read Timing W5 Address [A] ADV# [V] W2 CE# [ WE# [W] OE# [G] WAIT [T] Data [D/Q] W1 RST# [P] Figure 30: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address ...
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Figure 31: Write-to-Synchronous Read Timing CLK W5 Address [A] ADV# W2 CE# [ WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, ...
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P30 16.0 Program and Erase Characteristics Table 34: Program and Erase Specifications Num Symbol Parameter Single word - 130nm Program W200 t Single word - 65nm PROG/W Time Single cell W200 t Single word Program PROG/W Time W251 t 32-word ...
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... TE28F640P30T85 JS28F640P30B85 JS28F640P30T85 RC28F640P30B85 RC28F640P30T85 PC28F640P30B85 PC28F640P30T85 Datasheet 128-Mbit TE28F128P30B85 TE28F128P30T85 JS28F128P30B85 JS28F128P30T85 RC28F128P30B85 RC28F128P30T85 PC28F128P30B85 PC28F128P30T85 Access Speed 85 ns Parameter Location B = Bottom Parameter T = Top Parameter Product Fam ily P30 = Intel StrataFlash® Embedded Memory V = 1.7 – 2 1.7 – 3.6 V CCQ ...
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... Intel SCSP, lead-free RC = 64-Ball Easy BG A, leaded 64-Ball Easy BG A, lead-free 56-Lead TSO P , leaded JS = 56-Lead lead-free Group Designator 48F = Flash Memory only Flash Density die 2 = 64-Mbit 3 = 128-M bit 4 = 256-M bit Product Fam ily P = Intel StrataF lash® Em bedded M em ory ...
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... The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. ...
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... A_ID 00018h HI ... ... A.1.2 CFI Structure Overview The CFI command causes the flash component to display the Common Flash Interface (CFI) CFI structure or “database.” The structure sub-sections and address locations are summarized below. Table 39: CFI Structure Offset 00001-Fh Reserved 00010h CFI query identification string ...
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Table 41: System Interface Information Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 1 20h 1 21h 1 22h 1 23h 1 24h 1 25h 1 26h 1 Datasheet 72 Description V logic supply minimum program/erase voltage ...
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... August 2008 Order Number: 306666-12 Description n “n” such that device size = 2 in number of bytes Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table — — ...
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... Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Extended Flash Array Blocks supported bit 30 CFI Link(s) to follow bit 31 Another "Optional Features" field to follow (P+9)h 1 Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1– ...
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... Description (Optional flash features and commands) Page Mode Read capability n bits 0–7 = “n” such that 2 HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width ...
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... Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+ (Type n blocks)x(Type n block sizes) Datasheet 76 Description (Optional flash features and commands) Description (Optional flash features and commands) P30 See table below Address Bot Top Len 1 12D: ...
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... Control Mode invalid size in bytes (P+39)h (P+39)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) (P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information (P+3B)h (P+3B)h bits 0– y identical-size erase blks in a partition (P+3C)h (P+3C)h bits 16– region erase block(s) size are z x 256 bytes ...
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Table 49: Partition and Erase Block Region Information Address 64-Mbit –B 12D: --01 12E: --24 12F: --00 130: --01 131: --00 132: --11 133: --00 134: --00 135: --02 136: --03 137: --00 138: --80 139: --00 13A: --64 --00 ...
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... August 2008 Order Number: 306666-12 Description (Optional flash features and commands) 512-Mbit –B –T die 2 (T) die 1 (T) die 2 (B) --FF --10 --FF --FF --20 --FF --FF --00 --FF --FF --00 --FF --FF --10 --FF Hex Add. ...
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A.2 Flowcharts Figure 34: Word Program Flowchart Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status Register 1 SR[ ...
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P30 Figure 35: Program Suspend/Resume Flowchart Start Read Status Write 70 h Program Suspend Write B0h Any Address Read Status Register Read Array Write FFh Read Array Data Done No Reading Yes ...
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... Count ranges for this device are N = 0000h to 0001Fh. 2. The device outputs the status register when read. 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A address = 0) ...
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... SR[1] set = Locked Block NOTES: 1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary rite-buffer contents are programmed sequentially to the flash array starting at the first word address (W SM internally increments addressing ). August 2008 Order Number: 306666-12 Program & ...
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Figure 38: Block Erase Flowchart BLOCK ERASE PROCEDURE Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register No Suspend 0 Yes SR[7] = Erase 1 Full Erase Status Check (if desired) Block Erase ...
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P30 Figure 39: Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register 0 SR Erase 0 SR.6 = Completed 1 Read Read or ...
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Figure 40: Block Lock Operations Flowchart LOCKING OPERATIONS PROCEDURE Start Lock Setup Write 60 h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90 h Read Block Lock Status Locking No Change? Yes Read Array ...
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P30 Figure 41: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status Check (if desired) Program Complete FULL ...
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Figure 42: Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Program Ready Ready Setup Lock/CR Setup Ready (Lock Error) Setup OTP Busy Setup Busy Word Program Suspend ...
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P30 Figure 43: Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Setup Word Program Busy in Erase Suspend Busy Word Program in Erase Suspend Word Program Suspend ...
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Figure 44: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) OTP Ready Setup Ready Lock/CR Setup (Lock Error) Setup OTP Busy Setup Busy Word Program Suspend Setup BP Load 1 BP Confirm ...
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P30 Figure 45: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) Setup Busy Word Program in Erase Suspend Suspend Setup BP Load 1 BP Confirm if Data load into Program Buffer is ...
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Figure 46: Write State Machine—Next State Table (Sheet Output Next State Table Word Read Program (2) Array Setup (3,4) Current chip state (FFH) (10H/40H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, ...
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P30 Figure 47: Write State Machine—Next State Table (Sheet Output Next State Table Command Input to Chip and resulting Output Mux Next State OTP (4) Setup Current chip state (C0H) BEFP Setup, BEFP Pgm & Verify Busy, ...
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The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of ...
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P30 Appendix B Conventions - Additional Information B.1 Conventions VCC: Signal or voltage connection V : Signal or voltage level CC 0x: Hexadecimal number prefix 0b: Binary number prefix SR[4]: Denotes an individual register bit. A[15:0]: Denotes a group of ...
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... Numonyx™ Flash Memory. Datasheet 96 A group of bits, bytes, or words within the flash memory array that erase simultaneously. The P30 has two block sizes: 32 KByte and 128 KByte. An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks ...
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... Removed power supply sequencing requirement in and Power-Down” on page 50 Table 29, “Capacitance” on page 56 Updated conditions for Appendix A, “Common Flash Interface Tables” Updated CFI table in Table 14, “Device ID codes” on page 28 Added note to Device ID codes Synchronous burst read operation is currently not supported for the TSOP package Updated 512-Mbit Easy BGA Ball Height (symbol A1) in Mechanical Specifications” ...