71V256SA10Y IDT, Integrated Device Technology Inc, 71V256SA10Y Datasheet - Page 6

• Manufacturer Part Number: 71V256SA10Y
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 71V256SA10Y

• Density: 256Kb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 100mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
ADDRESS
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. t
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. t
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
ADDRESS
DATA
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
placed on the bus for the required t
spectified t
placed on the bus for the required t
spectified t
WR
WR
DATA
DATA
is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
OUT
WE
WE
CS
OE
CS
IN
IN
WP.
WP.
DW
DW
t
t
AS
AS
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
(3)
t
WHZ
(5)
t
t
AW
AW
t
t
t
WC
t
CW
WC
WP
6
(6)
(5)
t
DW
t
WP
WP
DATA VALID
DW
or (t
or (t
Commercial and Industrial Temperature Ranges
WHZ
WHZ
DATA VALID
+ t
+ t
DW
DW
t
t
DH
) to allow the I/O drivers to turn off and data to be
WR
) to allow the I/O drivers to turn off and data to be
t
t
WR
t
OW
t
DH
(5)
(1,2,4,6)
(1,2,3,4)
t
OHZ
(3)
(5)
3101 drw 09
3101 drw 10
,
,