HEF40175BT NXP Semiconductors, HEF40175BT Datasheet

HEF40175BT

Manufacturer Part Number
HEF40175BT
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of HEF40175BT

Logic Family
4000
Technology
CMOS
Number Of Bits
4
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Polarity
Invert/Non-Invert
Operating Supply Voltage (typ)
3.3/5/9/12V
Package Type
SO
Propagation Delay Time
160ns
Low Level Output Current
4.2mA
High Level Output Current
-4.2mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
15V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HEF40175BT
Manufacturer:
PANASONIC
Quantity:
100
Part Number:
HEF40175BT
Manufacturer:
PHI
Quantity:
1 000
Part Number:
HEF40175BT
Manufacturer:
NXP
Quantity:
2 500
Part Number:
HEF40175BT
Manufacturer:
NXP
Quantity:
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Part Number:
HEF40175BT
Manufacturer:
PHI
Quantity:
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1. General description
2. Features and benefits
3. Applications
4. Ordering information
Table 1.
All types operate from 40 C to +85 C.
Type number
HEF40175BP
HEF40175BT
HEF40175BTT
Ordering information
Package
Name
DIP16
SO16
TSSOP16
The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3),
a clock input (CP), an overriding asynchronous master reset input (MR), four buffered
outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on
D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR is HIGH.
When LOW, MR resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of
CP and D0 to D3.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over the full industrial (40 C to +85 C) temperature range.
HEF40175B
Quad D-type flip-flop
Rev. 6 — 14 December 2010
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
Industrial
Shift registers
Buffer/storage register
Pattern generator
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
SOT109-1
Version
SOT38-4
SOT403-1
SS

Related parts for HEF40175BT

HEF40175BT Summary of contents

Page 1

... All types operate from 40 C to +85 C. Type number Package Name HEF40175BP DIP16 HEF40175BT SO16 HEF40175BTT TSSOP16 DD Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm power supply range referenced another input ...

Page 2

... NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram CP MR Fig 2. Logic diagram HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2010 HEF40175B Quad D-type flip-flop 001aae569 001aae571 Q3 © NXP B.V. 2010. All rights reserved ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning HEF40175B 001aae570 Fig 3. Pin configuration SOT38-4 and SOT109-1 6.2 Pin description Table 2. Pin description Symbol Pin Functional description [1] Table 3. Function table Input CP Dn  H  L  HIGH voltage level LOW voltage level don’t care;  = positive-going transition;  = negative-going transition. ...

Page 4

... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current OK I input/output current I/O I supply current DD T storage temperature stg ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL HIGH-level output voltage  LOW-level output voltage  HIGH-level output current OH I LOW-level output current OL I input leakage current I I supply current ...

Page 6

... NXP Semiconductors Table 7. Dynamic characteristics = 25 C; for test circuit see amb Symbol Parameter Conditions t LOW to HIGH Qn; PLH propagation delay see MR to Qn; see t transition time see t t set-up time Dn to CP; su see t hold time Dn to CP; h see t pulse width; CP input LOW; W minimum pulse ...

Page 7

... NXP Semiconductors 12. Waveforms input input input PLH output and Propagation delays and Qn transition times CP input Dn input MR input b. Minimum pulse widths for CP and MR recovery time, and set-up and hold time for and V are typical output voltage levels that occur with the output load. ...

Page 8

... NXP Semiconductors a. Input waveforms b. Test circuit Test and measurement data is given in Definitions test circuit: DUT = Device Under Test Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance. L Fig 6. Test circuit for measuring switching times Table 9. Measurement points and test data ...

Page 9

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors 14. Revision history Table 10. Revision history Document ID Release date HEF40175B v.6 20101214 • Modifications: Added type number HEF40175BTT (SOT403-1 package). HEF40175B v.5 20100105 • Modifications: Section 2 “Features and benefits” HEF40175B v.4 20090813 HEF40175B_CNV v.3 19950101 HEF40175B_CNV v.2 19950101 HEF40175B ...

Page 13

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 14

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: HEF40175B Product data sheet 15 ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline ...

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