UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet
UPD78F0988AGC-8BS
Specifications of UPD78F0988AGC-8BS
Related parts for UPD78F0988AGC-8BS
UPD78F0988AGC-8BS Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual PD780988 Subseries 8-Bit Single-Chip Microcontrollers PD780982 PD780983 PD780984 PD780986 PD780988 PD78F0988A Document No. U13029EJ7V1UD00 (7th edition) Date Published August 2005 N CP(K) 1997, 2000, 2002 Printed in Japan PD780982(A) PD780983(A) PD780984(A) PD780986(A) PD780988(A) PD78F0988A(A) ...
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User’s Manual U13029EJ7V1UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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FIP and IEBus are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 Series ...
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These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. The information in this document is current as of July, 2005. ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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Major Revisions in This Edition (1/2) Page U13029JJ6V0UD00 U13029JJ7V0UD00 Throughout • Addition of package 64-pin plastic LQFP (14 x 14) PD780982GC- -8BS, 780983GC- PD780986GC- -8BS, 780988GC- PD780982GC(A)- PD780986GC(A)- • Change of power supply voltage range as shown below ...
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Major Revisions in This Edition (2/2) Page 12.4.2 Asynchronous serial interface (UART) mode p.234 • Modification of description p.235 • Modification of (1) Register setting (c) Baud rate generator control registers 0, 1 (BRGC00, BRGC01) p.240 Modification of Table 12-2 ...
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Target Readers This manual is intended for users who wish to understand the functions of the PD780988 Subseries and to design and develop application systems and programs using these microcontrollers. Purpose This manual is intended to give users an understanding ...
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Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices PD780988 Subseries User’s Manual ...
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Documents Related to Development Hardware Tools (User's Manuals) IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-78K0-NS-PA Performance Board IE-78001-R-A In-Circuit Emulator IE-78K0-R-EX1 In-Circuit Emulator Documents Related to Flash Memory Writing PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's ...
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CHAPTER 1 GENERAL ......................................................................................................................... 26 1.1 Expanded-Specification Products and Conventional Products ......................................... 26 1.2 Features ................................................................................................................................... 27 1.3 Applications ............................................................................................................................ 27 1.4 Ordering Information .............................................................................................................. 28 1.5 Pin Configuration (Top View) ................................................................................................. 30 1.6 78K/0 Series Lineup ................................................................................................................ 33 1.7 ...
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Processor Registers ............................................................................................................... 63 3.2.1 Control registers ............................................................................................................................. 63 3.2.2 General-purpose registers .............................................................................................................. 66 3.2.3 Special function registers (SFRs) ................................................................................................... 68 3.3 Instruction Address Addressing ........................................................................................... 73 3.3.1 Relative addressing ........................................................................................................................ 73 3.3.2 Immediate addressing .................................................................................................................... 74 3.3.3 Table ...
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Changing Setting of CPU Clock .......................................................................................... 104 5.6.1 Time required for switching CPU clock ......................................................................................... 104 5.6.2 Switching CPU clock ..................................................................................................................... 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER .................................................................................. 106 6.1 Outline of 16-Bit Timer/Event Counter ................................................................................ 106 6.2 Function ...
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Operation as watchdog timer ........................................................................................................ 178 9.5.2 Operation as interval timer ............................................................................................................ 179 CHAPTER 10 REAL-TIME OUTPUT PORT ........................................................................................ 180 10.1 Function of Real-Time Output Port ..................................................................................... 180 10.2 Configuration of Real-Time Output Port ............................................................................. 180 10.3 Registers Controlling ...
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Interrupt Servicing Operation .............................................................................................. 270 14.4.1 Non-maskable interrupt request acknowledgement operation ..................................................... 270 14.4.2 Maskable interrupt request acknowledgement operation ............................................................. 273 14.4.3 Software interrupt request acknowledgement operation .............................................................. 275 14.4.4 Multiple interrupt servicing ............................................................................................................ 276 14.4.5 Pending interrupt requests ...
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Description of flag operation column ............................................................................................ 344 19.2 Operation List ....................................................................................................................... 345 19.3 Instruction List by Addressing ............................................................................................ 353 CHAPTER 20 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS) ........ 357 CHAPTER 21 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) .......................... 377 CHAPTER 22 PACKAGE DRAWINGS ...
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Figure No. 2-1 Pin I/O Circuits ........................................................................................................................................ 47 3-1 Memory Map ( PD780982) .................................................................................................................... 49 3-2 Memory Map ( PD780983) .................................................................................................................... 50 3-3 Memory Map ( PD780984) .................................................................................................................... 51 3-4 Memory Map ( PD780986) .................................................................................................................... 52 3-5 Memory Map ( ...
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Figure No. 6-6 Format of Capture/Compare Control Register 01 ................................................................................. 114 6-7 Format of Timer Output Control Register 00 ......................................................................................... 115 6-8 Format of Timer Output Control Register 01 ......................................................................................... 116 6-9 Format of Prescaler Mode Register 00 ................................................................................................. 117 ...
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Figure No. 7-7 Format of Timer Clock Select Register 50 ............................................................................................ 146 7-8 Format of Timer Clock Select Register 51 ............................................................................................ 147 7-9 Format of Timer Clock Select Register 52 ............................................................................................ 147 7-10 Format of Port Mode Register 2 ........................................................................................................... ...
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Figure No. 11-5 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................. 210 11-6 A/D Conversion by Hardware Start (with Falling Edge Specified) ........................................................ 211 11-7 A/D Conversion by Software Start ........................................................................................................ 212 11-8 Example of Reducing Current Consumption ...
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Figure No. 14-4 Format of Priority Specification Flag Register ...................................................................................... 267 14-5 Format of External Interrupt Rising Edge Enable Register and External Interrupt Falling Edge Enable Register ................................................................................... 268 14-6 Format of External Interrupt Rising Edge Enable Register 5 and ...
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Figure No. 18-9 Signal Conflict (RESET Pin) ................................................................................................................. 314 18-10 Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O (SIO3) .............................................. 315 18-11 Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O (SIO3) with Handshake ................... 317 18-12 ...
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Table No. 1-1 Differences Between Expanded-Specification Products and Conventional Products............................. 26 1-2 Differences Between Standard Quality Grade Products and (A) Products ............................................. 38 1-3 Differences Between PD78F0988A and PD78F0988 ......................................................................... 38 2-1 Types of Pin I/O Circuits ......................................................................................................................... 46 3-1 ...
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Table No. 12-1 Configuration of Serial Interfaces ......................................................................................................... 223 12-2 Relationship Between Source Clock of 5-Bit Counter and Value of m (with UART00) ......................... 240 12-3 Relationship Between Source Clock of 5-Bit Counter and Value of m (with UART01) ......................... ...
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Expanded-Specification Products and Conventional Products The expanded-specification product and conventional product refer to the following products. Expanded-specification product: Products with a rank • Mask ROM versions for which orders were received after December 1, 2001. • Flash memory versions ...
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Features • Internal ROM and RAM Item Part Number Internal ROM PD780982 16 KB PD780983 24 KB PD780984 32 KB PD780986 48 KB PD780988 60 KB PD78F0988A Notes 1. 16, 24, 32, 48 are selectable by ...
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Ordering Information • Mask ROM products Part Number PD780982CW- PD780982CW- -A PD780982GC- -8BS PD780982GC- -8BS-A PD780983CW- PD780983CW- -A PD780983GC- -8BS PD780983GC- -8BS-A PD780984CW- PD780984CW- -A PD780984GC- -8BS PD780984GC- -8BS-A PD780986CW- PD780986CW- -A PD780986GC- -8BS PD780986GC- -8BS-A PD780988CW- PD780988CW- -A ...
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Flash Memory products Part Number PD78F0988ACW 64-pin plastic SDIP (19.05 mm (750)) PD78F0988ACW-A 64-pin plastic SDIP (19.05 mm (750)) PD78F0988AGC-AB8 64-pin plastic QFP (14 x 14) PD78F0988AGC-AB8-A 64-pin plastic QFP (14 x 14) PD78F0988AGC-8BS 64-pin plastic LQFP (14 x ...
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Pin Configuration (Top View) • 64-pin plastic SDIP (19.05 mm (750)) P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P51/SCK P52/SI P53/SO P54/TI000/TO00/INTP4 P55/TI010/INTP5 P56/TI001/TO01/INTP6 P57/TI011/INTP7 TO70 TO71 TO72 TO73 TO74 TO75 P20/RxD00 P21/TxD00 P22/RxD01 P23/TxD01 P24/TI50/TO50 P25/TI51/TO51 P26/TI52/TO52 ...
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QFP (14 x 14) • 64-pin plastic LQFP ( P50 1 P51/SCK 2 P52/SI 3 P53/SO 4 P54/TI000/TO00/INTP4 5 ...
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Remarks 1. The pin connection in parentheses is for the PD78F0988A. 2. When the PD780988 Subseries is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying ...
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Series Lineup The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Control PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 100-pin PD780058 80-pin PD78058F 80-pin PD78054 80-pin PD780065 ...
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The major functional differences among the subseries are listed below. Non-Y subseries Function ROM Capacity Subseries Name 8-Bit 16-Bit Watch WDT A/D (Bytes) Control PD78075B ...
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Y subseries ROM Function Capacity Subseries Name 8-Bit 16-Bit Watch WDT A/D (Bytes) Control PD78078Y PD78070AY – PD780018AY PD780058Y 24 ...
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Block Diagram TI000/TO00/INTP4/P54 16-bit timer/ event counter 00 TI010/INTP5/P55 TI001/TO01/INTP6/P56 16-bit timer/ event counter 01 TI011/INTP7/P57 8-bit timer/ TO50/TI50/P24 event counter 50 8-bit timer/ TO51/TI51/P25 event counter 51 8-bit timer/ TO52/TI52/P26 event counter 52 Watchdog timer RTP0/P30 to Real-time ...
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Functional Outline Part Number PD780982 Item Internal ROM Mask ROM memory 16 KB High-speed RAM 1024 bytes Expansion RAM None Memory space 64 KB General-purpose registers 8 bits 32 registers (8 bits Minimum instruction On-chip minimum instruction execution time ...
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The table below shows the outline of timer/event counters (for details, refer to CHAPTER 6 16-BIT TIMER/EVENT COUNTER, CHAPTER 7 8-BIT TIMER/EVENT COUNTER, CHAPTER 8 10-BIT INVERTER CONTROL TIMER, CHAPTER 9 WATCHDOG TIMER). Operation Interval timer Mode External event counter ...
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List of Pin Functions (1) Port pins Pin Name I/O P00 I/O Port 0 P01 4-bit I/O port P02 Input/output can be specified in 1-bit units. P03 Use of an on-chip pull-up resistor can be specified by a software ...
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Non-port pins (1/2) Pin Name I/O INTP0 Input External interrupt request input for which the valid edge (rising INTP1 edge, falling edge, or both rising and falling edges) can be INTP2 specified INTP3 INTP4 INTP5 INTP6 INTP7 TI50 Input ...
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Non-port pins (2/2) Pin Name I/O AV Input A/D converter reference voltage input REF AV – A/D converter analog power supply DD AV – A/D converter ground potential SS RESET Input System reset input X1 Input Connection of crystal ...
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Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port, port 0. In addition, these pins are also used to input external interrupt request signals, a timer output stop external signal and ...
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P20 to P26 (Port 2) These pins constitute a 7-bit I/O port, port 2. In addition, these pins are also used as the serial interface I/O pins, and the timer I/O pins. Port 2 can be set in the ...
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P50 to P57 (Port 5) These pins constitute an 8-bit I/O port, port 5. In addition, these pins also function as the serial interface clock and I/O, data I/O, timer I/O, and external interrupt request input pins. These pins ...
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Control mode In this mode, P64 to P67 function as control signal output pins (RD, WR, WAIT, and ASTB) in the external memory expansion mode. The pins used as control signal output pins are automatically disconnected from internal pull-up ...
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Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connections of unused pins are shown in Table 2-1. For each I/O circuit configuration, refer to Figure 2-1. Pin Name I/O ...
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TYPE 2 IN Schmitt-triggered input with hysteresis characteristics TYPE 4 V DD0 Data P-ch Output N-ch disable V SS0 Push/pull output that can become high impedance (off for both P-ch and N-ch) TYPE 5-H Pullup enable V DD0 Data P-ch ...
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CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Each product in the PD780988 Subseries can access a memory space of 64 KB. Figures 3-1 to 3-6 show the memory maps of the respective products. Cautions 1. The initial value of the ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map ( PD780982) FFFFH Special function registers (SFRs) FF00H FEFFH General-purpose registers FEE0H FEDFH Internal high-speed RAM 1,024 FB00H FAFFH Data memory space 4100H 40FFH External memory 4000H 3FFFH Program memory Internal ROM ...
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Figure 3-2. Memory Map ( PD780983) FFFFH FF00H FEFFH General-purpose registers FEE0H FEDFH Internal high-speed RAM FB00H FAFFH Data memory space 6100H 60FFH 6000H 5FFFH Program memory space 0000H 50 CHAPTER 3 CPU ARCHITECTURE Special function registers (SFRs) 256 8 ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( PD780984) FFFFH Special function registers (SFRs) FF00H FEFFH General-purpose registers FEE0H FEDFH Internal high-speed RAM 1,024 FB00H FAFFH Data memory space 8100H 80FFH External memory 8000H 7FFFH Program memory Internal ROM ...
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Figure 3-4. Memory Map ( PD780986) FFFFH FF00H FEFFH General-purpose registers FEE0H FEDFH Internal high-speed RAM FB00H FAFFH F800H F7FFH Data memory Internal expansion RAM space F400H F3FFH C100H C0FFH C000H BFFFH Program memory space 0000H 52 CHAPTER 3 CPU ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( PD780988) FFFFH Special function registers (SFRs) FF00H FEFFH General-purpose registers FEE0H FEDFH Internal high-speed RAM 1,024 FB00H FAFFH F800H F7FFH Data memory Internal expansion RAM space 1,024 F400H F3FFH F000H EFFFH ...
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Figure 3-6. Memory Map ( PD78F0988A) FFFFH FF00H FEFFH General-purpose registers FEE0H FEDFH Internal high-speed RAM FB00H FAFFH F800H F7FFH Data memory space Internal expansion RAM F400H F3FFH F000H EFFFH Program memory space 0000H 54 CHAPTER 3 CPU ARCHITECTURE Special ...
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Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). Each model in the PD780988 Subseries is provided with the following internal ROM (or flash ...
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CALLF instruction entry area A subroutine can be directly called from the area of addresses 0800H to 0FFFH by using a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space The PD780988 Subseries are provided with the following RAM. ...
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Data memory addressing The manner of specifying the address of the instruction to be executed next or specifying the address of a register or memory to be manipulated when an instruction is executed is called addressing. The address of ...
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Figure 3-8. Data Memory Addressing ( PD780983) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1,024 8 bits FE20H FE1FH FB00H FAFFH Reserved 6100H 60FFH External ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing ( PD780984) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1,024 8 bits FE20H FE1FH FB00H FAFFH ...
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Figure 3-10. Data Memory Addressing ( PD780986) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1,024 8 bits FE20H FE1FH FB00H FAFFH Reserved F800H F7FFH Internal ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data Memory Addressing ( PD780988) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1,024 8 bits FE20H FE1FH FB00H FAFFH ...
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Figure 3-12. Data Memory Addressing ( PD78F0988A) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1,024 8 bits FE20H FE1FH FB00H FAFFH Reserved F800H F7FFH Internal ...
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Processor Registers The PD780988 Subseries is provided with the following processor registers. 3.2.1 Control registers Each of these registers has a dedicated function such as to control the program sequence, status, and stack memory. The control registers include the ...
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Register bank select flags (RBS0 and RBS1) These 2-bit flags select one of the four register banks. 2-bit information indicating the register bank selected by execution of the “SEL RBn” instruction is stored in these flags. (d) Auxiliary carry ...
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Figure 3-16. Data Saved to Stack Memory PUSH rp instruction Register pair, low Register pair, high SP Figure 3-17. Data Restored from Stack Memory POP rp instruction SP Register ...
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General-purpose registers General-purpose registers are mapped to specific addresses of the data memory (FEE0H to FEFFH). Four banks of general-purpose registers, each consisting of eight 8-bit registers ( and H) are available. Each ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-18. General-Purpose Register Configuration FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H (a) Absolute name 16-bit processing RP3 RP2 ...
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Special function registers (SFRs) Unlike the general-purpose registers, special function registers have their own functions and are allocated to the area of addresses FF00H to FFFFH. The special function registers can also be manipulated in the same manner as ...
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Table 3-4. Special Function Register List (1/4) Address Special Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Port 5 FF06H Port 6 FF07H 8-bit timer counter 52 FF08H ...
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Table 3-4. Special Function Register List (2/4) Address Special Function Register (SFR) Name FF30H Pull-up resistor option register 0 FF32H Pull-up resistor option register 2 FF33H Pull-up resistor option register 3 FF34H Pull-up resistor option register 4 FF35H Pull-up resistor ...
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Table 3-4. Special Function Register List (3/4) Address Special Function Register (SFR) Name FF86H Real-time output port mode register 0 FF87H Real-time output port control register 0 FF89H Flash programming mode control register FF90H Inverter timer control register 7 FF91H ...
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Table 3-4. Special Function Register List (4/4) Address Special Function Register (SFR) Name FFE9H Priority specification flag register 0H FFEAH Priority specification flag register 1L FFF0H Memory size switching register FFF4H Internal expansion RAM size switching register FFF8H Memory extension ...
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Instruction Address Addressing An instruction address is determined by the contents of the program counter (PC). The contents of the PC are usually automatically incremented by the number of bytes of the instruction to be fetched (by 1 per ...
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Immediate addressing [Function] The immediate data in an instruction word is transferred to the program counter (PC), and program execution branches. This addressing is used when the “CALL !addr16”, “BR !addr16”, or “CALLF !addr11” instruction is executed. The CALL ...
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Table indirect addressing [Function] The contents of a specific location table (branch destination address) addressed by the immediate data of bits instruction code are transferred to the program counter (PC), and program execution branches. ...
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Register addressing [Function] The contents of the register pair (AX) specified by an instruction word are transferred to the program counter (PC), and program execution branches. This addressing is used when the “BR AX” instruction is executed. [Operation] 7 ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] This addressing is used to automatically (implicitly) address a register that functions as an ...
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Register addressing [Function] This addressing is used to access a general-purpose register as an operand. The general-purpose register to be accessed is specified by the register bank select flags (RBS0 and RBS1) and with the register specification code (Rn ...
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Direct addressing [Function] The addressing is used to directly address the memory indicated by the immediate data in an instruction word. [Operand Format] Representation addr16 [Example] MOV A, !0FE00H; To specify FE00H as !addr16 Instruction code [Operation] 7 CHAPTER ...
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Short direct addressing [Function] This addressing directly addresses a memory area to be manipulated from a fixed space by using the 8-bit data in an instruction word. This addressing is applicable to the fixed 256-byte space of FE20H to ...
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Special function register (SFR) addressing [Function] This addressing is to address special function registers (SFRs) mapped to the memory by using the 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte space of FF00H ...
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Register indirect addressing [Function] This addressing is used to address memory using the contents of a specified register pair as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) ...
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Based addressing [Function] This addressing is used to address the memory by using the result of adding 8-bit immediate data to the contents of the HL register pair used as a base register. The HL register pair to be ...
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Based indexed addressing [Function] This addressing is used to address the memory by using the result of adding the contents of the register specified in the instruction word to the contents of the HL register used ...
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Function of Ports The PD780988 Subseries is provided with eight input port pins and 39 I/O port pins. Figure 4-1 shows these port pins. Each port can be manipulated in 1-bit or 8-bit units and controlled in various ways. ...
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Pin Name 4-bit I/O port Port 0 P00 Input/output can be specified in 1-bit units. P01 Use of an on-chip pull-up resistor can be specified by a software setting. P02 P03 Port 1 P10 to P17 8-bit input-only port Port ...
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Configuration of Ports A port consists of the following hardware. Item Control registers Ports Total Input I/O Pull-up resistors 4.2.1 Port 0 This is a 4-bit I/O port with output latches. Port 0 can be set in the input ...
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Figure 4-2. Block Diagram of P00 to P03 WR PU PU00 to PU03 RD WR PORT Output latch (P00 to P03 PM00 to PM03 PU: Pull-up resistor option register PM: Port mode register RD: Read signal of port ...
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Port 2 This is a 7-bit I/O port with output latches. Port 2 can be set in the input or output mode in 1-bit units via port mode register 2 (PM2). When using port 2, internal pull-up resistors can ...
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Port 3 This is an 8-bit I/O port with output latches. Port 3 can be set in the input or output mode in 1-bit units via port mode register 3 (PM3). When using port 3, internal pull-up resistors can ...
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Port 4 This is an 8-bit I/O port with output latches. Port 4 can be set in the input or output mode in 1-bit units via port mode register 4 (PM4). When using port 4, internal pull-up resistors can ...
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Port 5 This is an 8-bit I/O port with output latches. Port 5 can be set in the input or output mode in 1-bit units via port mode register 5 (PM5). When using port 5, internal pull-up resistors can ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P51 to P57 WR PU PU51 to PU57 RD WR PORT Output latch (P51 to P57 PM51 to PM57 Alternate function PU: Pull-up resistor option register PM: Port mode ...
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Port 6 This is a 4-bit I/O port with output latches. Port 6 can be set in the input or output mode in 1-bit units via port mode register 6 (PM6). When using port 6, internal pull-up resistors can ...
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Registers Controlling Port Functions The following two types of registers control the ports. • Port mode registers (PM0, PM2, PM3, PM4, PM5, PM6) • Pull-up resistor option registers (PU0, PU2, PU3, PU4, PU5, PU6) (1) Port mode registers (PM0, ...
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Pull-up resistor option registers (PU0, PU2, PU3, PU4, PU5, PU6) These registers set whether the internal pull-up resistor is connected to each port. By setting PU0 and PU2 to PU6, on-chip pull-up resistors corresponding to bits in PU0 and ...
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Operation of Port Functions The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be ...
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CHAPTER 5 CLOCK GENERATOR 5.1 Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. Oscillation can be stopped by executing the STOP instruction. • Expanded-specification products The system oscillator oscillates ...
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Register Controlling Clock Generator The clock generator is controlled by the processor clock control register (PCC). This register selects the CPU clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to ...
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System Clock Oscillators 5.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator (12 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. ...
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CHAPTER 5 CLOCK GENERATOR Figure 5-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring SS1 (c) Wiring near high fluctuating current SS1 High Current User’s Manual U13029EJ7V1UD (b) Crossed signal line Pnm ...
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Figure 5-4. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched X2 X1 5.4.2 Divider The divider divides the output of the system clock oscillator (f 102 CHAPTER 5 CLOCK GENERATOR V SS1 ) to generate various clocks. X ...
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Operation of Clock Generator The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • System clock f X • CPU clock f CPU • Clock to peripheral hardware ...
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Changing Setting of CPU Clock 5.6.1 Time required for switching CPU clock The CPU clock can be selected by using bits (PCC0 to PCC2) of the processor clock control register (PCC). Actually, the specified clock is ...
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Switching CPU clock The following figure illustrates how the CPU clock is switched. Figure 5-5. Switching Between System Clock and CPU Clock V DD1 RESET CPU clock Internal reset operation <1> The CPU is reset when the RESET pin ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.1 Outline of 16-Bit Timer/Event Counter A 16-bit timer/event counter can be used as an interval timer, for PPG output, pulse width measurement (infrared remote control receive function external event counter, or for ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.3 Configuration of 16-Bit Timer/Event Counter A 16-bit timer/event counter includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter Item Timer register Register Timer output Control register Note Refer to Figure 4-8 Block ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-2. Block Diagram of 16-Bit Timer/Event Counter 01 Internal bus Capture/compare control register 01 (CRC01) CRC012 CRC011 CRC010 Noise elimi- TI011/P57/INTP7 nator Noise 4 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER • When CR00n is used as a compare register The value set in CR00n is constantly compared with the 16-bit timer counter 0n (TM0n) count value, and an interrupt request (INTTM00n) is generated if they ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) 16-bit capture/compare register 010, 011 (CR010, CR011) CR010 and CR011 are 16-bit registers that have the functions of both a capture register and a compare register. Whether to be used as a capture register ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-3. Format of 16-Bit Timer Mode Control Register 00 Symbol TMC00 Operating mode TMC003 TMC002 TMC001 and clear mode selection Operation stop 0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-4. Format of 16-Bit Timer Mode Control Register 01 Symbol TMC01 Operating mode TMC013 TMC012 TMC011 and clear mode selection Operation stop 0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) Capture/compare control register 00, 01 (CRC00, CRC01) These registers control the operation of the 16-bit capture/compare registers (CR000, CR010, CR001, CR011). CRC00 and CRC01 are set by a 1-bit or 8-bit memory manipulation instruction. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-6. Format of Capture/Compare Control Register 01 Symbol CRC01 CRC012 CR011 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC011 CR001 capture trigger ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) Timer output control register 00, 01 (TOC00, TOC01) These registers control the operation of the 16-bit timer/event counter 00, 01 output control circuit, including R- S type flip-flop (LV0) setting/resetting, output inversion enabling/disabling, and ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-8. Format of Timer Output Control Register 01 Symbol TOC01 TOC014 Timer output F/F control by match of CR011 and TM01 0 Inversion operation disabled 1 Inversion operation ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Prescaler mode register 00, 01 (PRM00, PRM01) This register is used to set the 16-bit timer counter 00, 01 (TM00, TM01) count clock and TI000, TI001 input valid edges. PRM00 and PRM01 are set ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-10. Format of Prescaler Mode Register 01 Symbol PRM01 ES111 ES110 ES011 ES111 ES110 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (5) Port mode register 5 (PM5) This register sets port 5 to input/output in 1-bit units. When using the P54/TO00/TI000/INTP4 pin or P56/TO01/TI001/INTP6 pin for timer output, set PM54 or PM56 and the output latch ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5 Operation of 16-Bit Timer/Event Counter 6.5.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-12 allows operation as an interval timer. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-13. Interval Timer Configuration Diagram Noise eliminator TI00n Remark Figure 6-14. Timing of Interval Timer Operation ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.2 PPG output operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-15 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-16. Configuration Diagram of PPG Output Remark Figure 6-17. PPG Output Operation Timing Count clock TM0n count value 0000H Count ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.3 Pulse width measurement operation It is possible to measure the pulse width of the signals input to the TI00n and TI01n pins using 16-bit timer counter 0n (TM0n). There are two measurement methods: measuring ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-19. Configuration Diagram for Pulse Width Measurement with Free-Running Counter TI00n Remark Figure 6-20. Timing of Pulse Width Measurement Operation ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode (see register settings in Figure 6-21 possible to simultaneously measure the pulse widths ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER • Capture operation (Free-running mode) The capture register operation of when the capture trigger is input is shown. Figure 6-22. CR01n Capture Operation with Rising Edge Specified Count clock TM0n TI00n Rising edge detection CR01n ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode (see register settings in Figure 6-24 possible to measure the pulse ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-25. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM0n 0000H 0001H D0 count value TI00n pin input Value loaded to CR01n ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0n (TMC0n) TMC0n (b) Capture/compare control register 0n (CRC0n) CRC0n 0 0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00n pin by 16-bit timer counter 0n (TM0n). TM0n is incremented each time the ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-29. External Event Counter Configuration Diagram Noise eliminator X Valid edge of TI00n Noise eliminator Remark Figure ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-31. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n (b) Capture/compare control register 0n (CRC0n) CRC0n ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.6 Notes on 16-Bit Timer/Event Counter (1) Timer start errors An error of a maximum of one clock may occur during the time required for a match signal to be generated after timer start. This ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timing If the valid edge of the TI00n pin is input during 16-bit capture/compare register 01n (CR01n) read, CR01n performs a capture operation, but the capture value at this time ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (6) Operation of OVF0n flag <1> The OVF0n flag (bit 6 of 16-bit timer mode control register 0n (TMC0n)) is set to 1 the next time. One of clear & start mode entered on match ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (8) Timer operation <1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured in 16-bit capture/compare register 01n (CR01n). <2> Regardless of the operation mode of the CPU, if the ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1 Outline of 8-Bit Timer/Event Counter An 8-bit timer/event counter can be used as an interval timer, external event counter, to output a square wave with any selected frequency, and for PWM output. Two 8-bit ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.3 Configuration of 8-Bit Timer/Event Counter An 8-bit timer/event counter includes the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counter Item Timer register Register Timer output Control registers Note Refer to Figure 4-4 Block ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51 8-bit compare register 51 (CR51) TI51/TO51/P25 Match 8-bit timer X counter (TM51) 4 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (1) 8-bit timer counters 50, 51, and 52 (TM50, TM51, and TM52) TM50, TM51, and TM52 are 8-bit read-only registers that count count pulses. These counters are incremented in synchronization with the rising edge of ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4 Registers Controlling 8-Bit Timer/Event Counter The following seven registers control 8-bit timer/event counters 50, 51, and 52. • 8-bit timer mode control registers 50, 51, and 52 (TMC50, TMC51, and TMC52) • Timer clock ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-4. Format of 8-Bit Timer Mode Control Register 50 Symbol TMC50 TCE50 TMC506 0 0 TCE50 TM50 count operation control 0 Disables count operation after clearing counter to 0 (disables ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-5. Format of 8-Bit Timer Mode Control Register 51 Symbol TMC51 TCE51 TMC516 0 TCE51 TM51 count operation control 0 Disables count operation after clearing counter to 0 (disables prescaler). 1 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-6. Format of 8-Bit Timer Mode Control Register 52 Symbol TMC52 TCE52 TMC526 0 TCE52 TM52 count operation control 0 Disables count operation after clearing counter to 0 (disables prescaler). 1 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) Timer clock select registers 50, 51, and 52 (TCL50, TCL51, and TCL52) These registers specify the count clock of 8-bit timer counters 50, 51, and 52 (TM50, TM51, and TM52) and the valid edges ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-8. Format of Timer Clock Select Register 51 Symbol TCL51 TCL512 TCL511 TCL510 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) Port mode register 2 (PM2) This register sets port 2 in the input or output mode in 1-bit units. When the P24/TI50/TO50 to P26/TI52/TO52 pins are used for timer output, clear PM24 to PM26 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5 Operation of 8-Bit Timer/Event Counter 7.5.1 Interval timer (8-bit) operation The 8-bit timer/event counters operate as interval timers that repeatedly generate an interrupt request at time intervals specified by the count values preset to ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-11. Interval Timer Operation Timing (2/3) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n TO5n (c) When CR5n = FFH t Count clock TM5n 01H CR5n FFH TCE5n INTTM5n TO5n Remark ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-11. Interval Timer Operation Timing (3/3) (d) Operation when CR5n is changed (M < N) Count clock TM5n N 00H CR5n N TCE5n H INTTM5n TO5n (e) Operation when CR5n is changed (M > ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5.2 External event counter operation The external event counter counts the number of clock pulses externally input to the TI50/P24 to TI52/P26 pins by using 8-bit timer counter 5n (TM5n). Each time the valid edge ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5.3 Square-wave output (8-bit resolution) operation The 8-bit timer/event counters operate as a square wave output at the interval preset to 8-bit compare register 5n (CR5n). When bit 0 (TOE5n) of 8-bit timer mode control ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5.4 8-bit PWM output operation The PWM output operation is performed when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set pulse with a duty factor determined by ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-14. PWM Output Operation Timing (a) Basic operation (when active level = H) Count clock TM5n 00H 01H FFH 00H CR5n N TCE5n INTTM5n TO5n (b) When CR5n = 0 Count clock TM5n 00H ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) Operation when CR5n is changed Figure 7-15. Operation Timing When CR5n Is Changed (a) If value of CR5n is changed from before TM5n overflows Count clock TM5n ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5.5 Interval timer (16-bit) operation (1) Cascade (16-bit timer) mode (TM50 and TM51) The 16-bit resolution timer/event counter mode is set by setting bit 4 (TMC514) of 8-bit timer mode control register 51 (TMC51) to ...
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Cascade (16-bit timer) mode (TM51 and TM52) The 16-bit resolution timer/event counter mode is set by setting bit 4 (TMC524) of 8-bit timer mode control register 52 (TMC52 this mode, TM51 and TM52 operate as a ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.6 Notes on 8-Bit Timer/Event Counter (1) Error on starting timer An error clock occurs after the timer has been started until a match signal is generated. This is because 8-bit ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER 8.1 Outline of 10-Bit Inverter Control Timer The 10-bit inverter control timer makes inverter control possible. It consists of an 8-bit dead-time generation timer, and allows non-overlapping active-level output. 8.2 Function of 10-Bit Inverter ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER Figure 8-1. Block Diagram of 10-Bit Inverter Control Timer TM7 BFCM3 CM3 ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER (3) 10-bit compare register 3 (CM3) CM3 is a 10-bit compare register that controls the high limit value of TM7. If the count value of TM7 matches the value of CM3 or 0, count ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER 8.4 Registers Controlling 10-Bit Inverter Control Timer The following two registers control the 10-bit inverter control timer. • Inverter timer control register 7 (TMC7) • Inverter timer mode register 7 (TMM7) (1) Inverter timer ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER Figure 8-2. Format of Inverter Timer Control Register Symbol TMC7 CE7 0 TCL72 TCL71 TCL70 IDEV2 IDEV1 IDEV0 CE7 0 Clear and stop (TO70 to TO75 are Hi-Z) 1 Count ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER (2) Inverter timer mode register 7 (TMM7) TMM7 controls the operation of and specifies the active level of the TO70 to TO75 outputs, and sets the valid edge of TOFF7. TMM7 is set by ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER Remarks 1. TO70 to TO75 become Hi-Z state in the following cases. However, the TM7, DTM0 to DTM2, and RTM0 timers do not stop if CE7 = 1 is set. • A valid edge ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER 8.5 Operation of 10-Bit Inverter Control Timer (1) Setting procedure (a) The TM7 count clock is set with the TCL70 to TCL72 bits of inverter timer control register 7 (TMC7) and the occurrence frequency ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER (2) Output waveform widths corresponding to set values • PWM cycle = CM3 2 T • Dead-time width = T = (DTIME + 1) DTM • Active width of positive phase (TO70, TO72, TO74 ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER (3) Operation timing Figure 8-4. TM7 Operation Timing (Basic Operation) TM7 a 0 BFCMn CMn BFCM3 CM3 F/F DTMn TO70, TO72, TO74 TO71, TO73, TO75 t Remarks ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER Figure 8-5. TM7 Operation Timing (CMn (BFCMn) TM7 a 0 BFCMn CMn BFCM3 CM3 F/F DTMn TO70, TO72, TO74 TO71, TO73, TO75 t Remarks Dead time ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER Figure 8-6. TM7 Operation Timing (CMn (BFCMn) = 000H) X TM7 a 0 BFCMn b a CMn BFCM3 Y X CM3 F/F DTMn TO70, TO72, TO74 TO71, TO73, TO75 t Remarks ...
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER Figure 8-7. TM7 Operation Timing (CMn (BFCMn) = CM3 – 1/2DTM, CMn (BFCMn) > CM3 – 1/2DTM) a TM7 0 BFCMn – —DTM) CMn 2 BFCM3 CM3 F/F DTMn TO70, ...
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CHAPTER 9 WATCHDOG TIMER 9.1 Outline of Watchdog Timer The watchdog timer can also be used to generate a non-maskable interrupt request, maskable interrupt request, or RESET signal at preset time intervals. 9.2 Function of Watchdog Timer The watchdog timer ...
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Interval timer mode When the watchdog timer is used as an interval timer, it generates an interrupt request at preset time intervals. Note Interval Time MHz 1/f 341 ...
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Registers Controlling Watchdog Timer The following three registers control the watchdog timer. • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) • Oscillation stabilization time select register (OSTS) (1) Watchdog timer clock select register (WDCS) ...
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Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to ...
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Oscillation stabilization time select register (OSTS) This register selects the oscillation stabilization time that elapses after the RESET signal is applied or the STOP mode is released, until oscillation is stabilized. OSTS is set by an 8-bit memory manipulation ...
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Operation of Watchdog Timer 9.5.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The loop detection time interval of the ...
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Operation as interval timer When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0, the watchdog timer operates as an interval timer that repeatedly generates an interrupt request at time intervals specified by a ...
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CHAPTER 10 REAL-TIME OUTPUT PORT 10.1 Function of Real-Time Output Port Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupts or external interrupt request generation, then output ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-1. Block Diagram of Real-Time Output Port (1/2) (a) Real-time output port 0 (8 bits Real-time output port control register 0 (RTPC00) RTPOE00 RTPEG00 BYTE00 EXTR00 4 INTP2 (from outside) Output trigger INTTM000 (from ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-1. Block Diagram of Real-Time Output Port (2/2) (b) Real-time output port 1 (6 bits Real-time output port control register 1 (RTPC01) RTPOE01 BYTE01 2 Output trigger INTTM001 (from TM01) controller TO7n (from TM7) ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (1) Real-time output buffer register 0 (RTBL00, RTBH00) This register consists of two 4-bit registers that hold output data in advance. The addresses of RTBL00 and RTBH00 are mapped individually in the special function register ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (2) Real-time output buffer register 1 (RTBL01, RTBH01) This register consists of two 4-bit The addresses of RTBL01 and RTBH01 are mapped individually in the special function register (SFR) area as shown in Figure 10-3. ...
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CHAPTER 10 REAL-TIME OUTPUT PORT 10.3 Registers Controlling Real-Time Output Port The following seven types of registers control the real-time output ports. • Port mode register 3 (PM3) • Real-time output port mode register 0, 1 (RTPM00, RTPM01) • Real-time ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (3) Real-time output port mode register 1 (RTPM01) This register sets the real-time output port mode in 1-bit units. The output is TO70 to TO75. RTPM01 is set by a 1-bit or 8-bit memory manipulation ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (4) Real-time output port control register 0 (RTPC00) This register is used to set the operation mode, output trigger and operation enable/disable of the real-time output port. The output is RTP0 to RTP7. The relationship ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (5) Real-time output port control register 1 (RTPC01) This register is used to set the operation mode, and enabling or disabling operation of the real-time output port. The output is TO70 to TO75. The relationship ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (6) DC control register 0 (DCCTL0) This register is used to enable/disable PWM modulation, and enable/disable inversion of the output waveform of the real-time output port. The output is RTP0 to RTP7. DCCTL0 is set ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (7) DC control register 1 (DCCTL1) This register is used to enable/disable PWM modulation, and enable/disable inversion of the output waveform of the real-time output port. The output is TO70 to TO75. DCCTL1 is set ...
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CHAPTER 10 REAL-TIME OUTPUT PORT 10.4 Operation of Real-Time Output Port (1) Using RTP0 to RTP7 as the real-time output port ..... Real-time output port 0 (8 bits bits 2) When bit 7 (RTPOE00) of real-time output ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Table 10-6. Relationship Between Settings of Each Bit of Control Register and Real-Time Output PM3n P3n DCEN0 PM3n: Bit n of port mode register 3 (PM3) P3n: Bit n ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-11. Real-Time Output Port Operation Timing Example (8 Bits (a) 8 bits 1 channel, inverted output disabled, no PWM modulation (EXTR00 = 0, BYTE00 = 1, INV0 = 0, PWMCH0 = 0, PWMCL0 = ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-11. Real-Time Output Port Operation Timing Example (8 Bits (b) 8 bits 1 channel, inverted output enabled, no PWM modulation (EXTR00 = 0, BYTE00 = 1, INV0 = 1, PWMCH0 = 0, PWMCL0 = ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-11. Real-Time Output Port Operation Timing Example (8 Bits (c) 8 bits 1 channel, inverted output enabled, PWM modulation (EXTR00 = 0, BYTE00 = 1, INV0 = 1, PWMCH0 = 1, PWMCL0 = 1) ...
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CHAPTER 10 REAL-TIME OUTPUT PORT (2) Using TO70 to TO75 as a real-time output port ..... Real-time output port 1 (6 bits bits 1) If real-time output is enabled when bit 7 (RTPOE01) of real-time output port ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Table 10-7. Relationship Between Settings of Each Bit of Control Register and Real-Time Output CE7 DCEN1 INV1 PWMCH1/ PWMCL1 CE7: Bit 7 of inverter timer ...
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CHAPTER 10 REAL-TIME OUTPUT PORT Figure 10-12. Real-Time Output Port Operation Timing Example (6 Bits (a) 6 bits 1 channel, inverted output disabled, no PWM modulation (BYTE01 = 1, INV1 = 0, PWMCH1 = 0, PWMCL1 = 0) INTTM001 CPU ...