K4S641632H-TC60 Samsung Semiconductor, K4S641632H-TC60 Datasheet
K4S641632H-TC60
Specifications of K4S641632H-TC60
Available stocks
Related parts for K4S641632H-TC60
K4S641632H-TC60 Summary of contents
Page 1
... SDRAM 64Mb H-die (x4, x8, x16) 64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free * Samsung Electronics reserves the right to change products or specification without notice. (RoHS compliant) Revision 1.3 August 2004 CMOS SDRAM Rev. 1.3 August 2004 ...
Page 2
... SDRAM 64Mb H-die (x4, x8, x16) Revision History Revision 1.0 (September, 2003) • Finalized Revision 1.1 (October, 2003) Deleted speed -7C and AC parameter notes 5. Revision 1.2 (May, 2004) • Added Note 5. sentense of tRDL parameter Revision 1.3 (August, 2004) • Corrected typo. CMOS SDRAM ...
Page 3
... RoHS compliant GENERAL DESCRIPTION The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized 4,194,304 words by 4 bits 2,097,152 words by 8 bits 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high perfor- mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
Page 4
... SDRAM 64Mb H-die (x4, x8, x16) Package Physical Dimension #54 #1 0.10 MAX 0.004 0. 0.028 #28 #27 22.62 MAX 0.891 22.22 ± 0.10 ± 0.004 0.875 0.008 +0.10 0.30 0.80 -0.05 +0.004 0.0315 0.012 -0.002 54Pin TSOP(II) Package Dimension CMOS SDRAM 0~8°C 0.25 TYP 0 ...
Page 5
... SDRAM 64Mb H-die (x4, x8, x16) FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE Samsung Electronics reserves the right to change products or specification without notice. * Data Input Register Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register ...
Page 6
... SDRAM 64Mb H-die (x4, x8, x16) PIN CONFIGURATION (Top view) x8 x16 DQ0 DQ0 V V DDQ DDQ DQ1 N.C DQ2 DQ1 V V SSQ SSQ DQ3 N.C DQ4 DQ2 V V DDQ DDQ DQ5 N.C DQ6 DQ3 V V SSQ SSQ DQ7 N LDQM N CAS CAS RAS ...
Page 7
... SDRAM 64Mb H-die (x4, x8, x16) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. ...
Page 8
... SDRAM 64Mb H-die (x4, x8, x16) DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (One bank active) I CC2 Precharge standby current in power-down mode I CC2 I CC2 Precharge standby current in non power-down mode I CC2 I CC3 Active standby current in power-down mode ...
Page 9
... Operating current I CC4 (Burst mode) Refresh current I CC5 Self refresh current I CC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632H-TC** 4. K4S641632H-TL** 5. Unless otherwise noted, input swing IeveI is CMOS 70°C for x16 only) A Test Condition Burst length = 1 ≥ (min CKE ≤ V ...
Page 10
... SDRAM 64Mb H-die (x4, x8, x16) AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V Output 870Ω (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...
Page 11
... SDRAM 64Mb H-die (x4, x8, x16) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width CLK low pulse width ...
Page 12
... SDRAM 64Mb H-die (x4, x8, x16) IBIS SPECIFICATION I Characteristics (Pull-up) OH 133MHz Voltage Min (V) I (mA) 3.45 - 3.30 - 3.00 -0.35 2.70 -3.75 2.50 -6.65 1.95 -13.75 1.80 -17.75 1.65 -20.55 1.50 -23.55 1.40 -26.2 1.00 -36.25 0.20 -46.5 I Characteristics (Pull-down) OL 133MHz Voltage Min (V) I (mA) 3 ...
Page 13
... SDRAM 64Mb H-die (x4, x8, x16) V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15 ...
Page 14
... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...