CY7C0831AV-133BBI Cypress Semiconductor Corp, CY7C0831AV-133BBI Datasheet

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... TQFP 120 TQFP 120 TQFP 144 FBGA 144 FBGA 144 FBGA • 198 Champion Court • San Jose CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [16] on page 6 4 Mbit 9 Mbit (256K x 18) (512K x 18) [1] CY7C0832BV CY7C0833AV 167 133 133 4 ...

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... Mirror Reg CLK L CNTINT L Interrupt INT L Logic Note 2. CY7C0837AV has 15 address bits, CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV/CY7C0832BV has 18 address bits and CY7C0833AV has 19 address bits. Document #: 38-06059 Rev. *S I/O I/O Control Control True Dual-Ported RAM Array Address ...

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... Leave this ball unconnected for CY7C0837AV and CY7C0830AV. 5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV. 6. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV, and CY7C0832AV. 7. These balls are not applicable for CY7C0833AV device. They must be tied to VDD. 8. These balls are not applicable for CY7C0833AV device. They must be tied to VSS. ...

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... R CLK ADS L 19 CNTEN 20 L CNTRST 21 L CNT/MSK 10L 11L A 27 12L 13L Notes 10. Leave this pin unconnected for CY7C0830AV. 11. Leave this pin unconnected for CY7C0830AV and CY7C0831AV. Document #: 38-06059 Rev. *S CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV R CLK R 73 MRST 72 ADS ...

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... JTAG TAP. V Ground Inputs Power Inputs. DD Byte Select Operation Control Pin Document #: 38-06059 Rev. *S CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Description . MAX is asserted LOW when the L Effect DQ Byte Control 0–8 DQ Byte Control 9–17 Page ...

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... At least one of BE0, BE1 must be LOW. 15. A18x for CY7C0832AV/CY7C0832BV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the Interrupt addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830AV, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x and A15x are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE ...

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... L L Mask Load L H Mask Readback H X Reserved CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 3 on page 9 shows a [17, 18] Description Reset address counter to all 0s and mask register to all 1s. Reset counter unmasked portion to all 0s. Load counter with external address value presented on address lines. ...

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... This even-odd address scheme stores one half of the 36-bit data in even memory locations, and the other half in odd memory locations. n – – 2. From the CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 3 on page 9 shows a Page CM2 [+] Feedback ...

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... Increment Mask Register 17 From Mask 17 From +1 Counter +2 Document #: 38-06059 Rev. *S Mask Register Counter/ Address Register Load/Increment Mirror Counter Logic Wrap 17 Bit 0 Wrap 1 Detect CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [1] Address RAM Decode Array To Readback and Address Decode 17 Wrap To Counter Page [+] Feedback ...

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... Further information is found in the Cypress application note Scan For System in a Package (SIP) Dual-Port Performing a Pause/Restart on page 10 for deviation from strict 1149.1 compliance CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [2, 20 ...

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... TDI TDI Reserved for version number. Defines Cypress part number for CY7C0832AV/CY7C0832BV Defines Cypress part number for CY7C0831AV Defines Cypress part number for CY7C0830AV Defines Cypress part number for CY7C0837AV. Allows unique identification of the DP family device vendor. Indicates the presence register. ...

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... OUT Parameter Description C Input Capacitance IN C Output Capacitance OUT C Input Capacitance IN C Output Capacitance OUT CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Ambient V DD Temperature 0°C to +70°C 3.3V±165 mV –40°C to +85°C 3.3V±165 mV -133 -100 Typ Max Min Typ Max 2 ...

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... CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV 3. 590 Ω 435 Ω 90% 10% < -133 -100 CY7C0833AV CY7C0833AV Unit Min Max Min Max 133 100 MHz 7 ...

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... RSF t Master Reset to Counter Interrupt Flag RSCNTINT Reset Time Notes 28. This parameter is guaranteed by design, but is not production tested. 29. Test conditions used are Load 2. Document #: 38-06059 Rev. *S CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV -167 -133 CY7C0837AV CY7C0837AV CY7C0830AV CY7C0830AV CY7C0831AV CY7C0833AV CY7C0831AV ...

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... TCK Clock LOW to TDO Valid TDOV t TCK Clock LOW to TDO Invalid TDOX Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-06059 Rev. *S CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Description Figure 7. JTAG Switching Waveform TMSS t TMSH t TDIS ...

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... Figure 9. Read Cycle t CL2 A A n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V constantly loads the address on the rising edge of the CLK CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV n n+1 n+2 t OHZ t OLZ t OE Page ...

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... Figure 10. Bank Select Read CD2 CD2 HC CKHZ CD2 t CKLZ [33, 36, 37, 38, 39 n+1 n CD2 CKHZ Q n READ NO OPERATION WRITE CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV CD2 CKHZ CKLZ CKHZ CD2 CKLZ A A n+3 n+4 t CD2 Q n+3 t CKLZ READ Page (B1) [+] Feedback ...

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... Document #: 38-06059 Rev n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [33, 36, 38, 39 n+4 n+5 t CD2 Q READ [38] t HAD t HCN Q n+2 READ WITH COUNTER Page n+4 Q n+3 [+] Feedback ...

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... Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06059 Rev n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD [40, 41] Figure 15. Counter Reset CD2 t CKLZ WRITE READ READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [39 n+2 n+3 n n+3 n+4 WRITE WITH COUNTER CD2 Q ...

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... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06059 Rev CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [43, 44, 45, 46 n+4 n+2 n n+1 n+2 n+3 Page [+] Feedback ...

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... HD CKLZ n t CCS CD2 CNTRST = MRST = CNT/MSK = HIGH CYC2 CD2 CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [47, 48, 49 violated, indeterminate data is Read out. CCS + t ) after the rising edge of R_Port's clock CYC2 CD2 ) after the rising edge of R_Port's clock. Page CCS [+] Feedback ...

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... CNTINT is always driven. 52. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 53. The mask register assumed to have the value of 3FFFFh. Document #: 38-06059 Rev. *S CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [15, 42, 50, 51, 52, 53] 3FFFE 3FFFF Last_Loaded ...

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... R/W = HIGH Document #: 38-06059 Rev. *S [54, 55, 56, 57 SINT t RINT 7FFFF m m+1 [2, 17, 59, 60, 61] Outputs CE R/W DQ – High High OUT H X High-Z CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV A A n+2 n m+3 m+4 Operation 17 Deselected Deselected Write Read Outputs Disabled Page [+] Feedback ...

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... CY7C0831AV-133BBC 51-85141 144-Ball Grid Array ( 1.6 mm) with 1 mm pitch CY7C0831AV-133BBXC CY7C0831AV-133AC 51-85100 120-Pin Thin Quad Flat Pack ( 1.4 mm) CY7C0831AV-133AXC CY7C0831AV-133BBI 51-85141 144-Ball Grid Array ( 1.6 mm) with 1 mm pitch CY7C0831AV-133BBXI CY7C0831AV-133AI 51-85100 120-Pin Thin Quad Flat Pack ( 1.4 mm) CY7C0831AV-133AXI 64K × 18 (1M) 3.3V Synchronous CY7C0830AV Dual-Port SRAM ...

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... Grid Array ( 1.6 mm) with 1 mm pitch Package Diagrams Figure 20. 144-Ball FBGA ( 1.6 mm) (51-85141) TOP VIEW A1 CORNER 13.00±0.10 SEATING PLANE C Document #: 38-06059 Rev. *S CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Package Type BOTTOM VIEW Ø0. Ø0. +0.10 Ø0.50 (144X) -0. 5.50 A 1.00 11.00 13.00± ...

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... Package Diagrams Figure 21. 120-Pin Thin Quad Flatpack ( 1.4 mm) (51-85100) Document #: 38-06059 Rev. *S CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV 51-85100-** Page [+] Feedback ...

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... Document History Page Document Title: CY7C0837AV/CY7C0830AV/CY7C0831AV/CY7C0832AV/CY7C0832BV/CY7C0833AV, FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Document Number: 38-06059 Orig. of Submission Rev. ECN No. Change ** 111473 DSG *A 111942 JFU *B 113741 KRE *C 114704 KRE *D 115336 KRE *E 122307 RBI *F 123636 KRE *G 126053 SPN ...

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... FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b USB Revised March 03, 2009 CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...