MC68HC11E1CFU3 Freescale Semiconductor, MC68HC11E1CFU3 Datasheet - Page 29
MC68HC11E1CFU3
Manufacturer Part Number
MC68HC11E1CFU3
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC11E1CFU3.pdf
(242 pages)
Specifications of MC68HC11E1CFU3
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
3MHz
Interface Type
SCI/SPI
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Chapter 2
Operating Modes and On-Chip Memory
2.1 Introduction
This section contains information about the operating modes and the on-chip memory for M68HC11
E-series MCUs. Except for a few minor differences, operation is identical for all devices in the E series.
Differences are noted where necessary.
2.2 Operating Modes
The values of the mode select inputs MODB and MODA during reset determine the operating mode.
Single-chip and expanded multiplexed are the normal modes.
Each of the two normal modes is paired with a special mode:
2.2.1 Single-Chip Mode
In single-chip mode, ports B and C and strobe pins A (STRA) and B (STRB) are available for
general-purpose parallel input/output (I/O). In this mode, all software needed to control the MCU is
contained in internal resources. If present, read-only memory (ROM) and/or erasable, programmable
read-only memory (EPROM) will always be enabled out of reset, ensuring that the reset and interrupt
vectors will be available at locations $FFC0–$FFFF.
2.2.2 Expanded Mode
In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includes:
The expansion bus is made up of ports B and C, and control signals AS (address strobe) and R/W
(read/write). R/W and AS allow the low-order address and the 8-bit data bus to be multiplexed on the
same pins. During the first half of each bus cycle address information is present. During the second half
of each bus cycle the pins become the bidirectional data bus. AS is an active-high latch enable signal for
an external address latch. Address information is allowed through the transparent latch while AS is high
and is latched when AS drives low.
Freescale Semiconductor
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In single-chip mode only on-chip memory is available.
Expanded mode, however, allows access to external memory.
Bootstrap, a variation of the single-chip mode, is a special mode that executes a bootloader
program in an internal bootstrap ROM.
Test is a special mode that allows privileged access to internal resources.
The same on-chip memory addresses used for single-chip mode
Addresses for external peripherals and memory devices
For the MC68HC811E2, the vector locations are the same; however, they
are contained in the 2048-byte EEPROM array.
M68HC11E Family Data Sheet, Rev. 5.1
NOTE
29
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