MC68HC11E1CFU3 Freescale Semiconductor, MC68HC11E1CFU3 Datasheet - Page 68

MC68HC11E1CFU3

Manufacturer Part Number
MC68HC11E1CFU3
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC11E1CFU3

Cpu Family
HC11
Device Core Size
8b
Frequency (max)
3MHz
Interface Type
SCI/SPI
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFU3
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC68HC11E1CFU3
Quantity:
5 510
Part Number:
MC68HC11E1CFU3
Manufacturer:
CY
Quantity:
118
Part Number:
MC68HC11E1CFU3
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
4.2.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction to be executed. After
reset, the program counter is initialized from one of six possible vectors, depending on operating mode
and the cause of reset. See
4.2.6 Condition Code Register (CCR)
This 8-bit register contains:
In the M68HC11 CPU, condition codes are updated automatically by most instructions. For example, load
accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the N, Z,
and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to
affected by a particular instruction.
4.2.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic operation.
The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate
with and through the carry bit to facilitate multiple-word shift operations.
4.2.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V bit is cleared.
4.2.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is 0. Otherwise, the Z
bit is cleared. Compare instructions do an internal implied subtraction and the condition codes, including
Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and
no other condition flags. For these operations, only = and ≠ conditions can be determined.
4.2.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1).
Otherwise, the N bit is cleared. A result is said to be negative if its most significant bit (MSB) is a 1. A quick
way to test whether the contents of a memory location has the MSB set is to load it into an accumulator
and then check the status of the N bit.
68
Central Processor Unit (CPU)
Five condition code indicators (C, V, Z, N, and H),
Two interrupt masking bits (IRQ and XIRQ)
A stop disable bit (S)
Test or Boot
Normal
Mode
Table
POR or RESET Pin
Table 4-1. Reset Vector Comparison
4-1.
M68HC11E Family Data Sheet, Rev. 5.1
$BFFE, F
$FFFE, F
Table
Clock Monitor
$BFFC, D
$FFFC, D
4-2, which shows what condition codes are
COP Watchdog
$FFFA, B
$BFFA, B
Freescale Semiconductor

Related parts for MC68HC11E1CFU3