MCM67Q709AZP10 Freescale Semiconductor, MCM67Q709AZP10 Datasheet

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MCM67Q709AZP10

Manufacturer Part Number
MCM67Q709AZP10
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MCM67Q709AZP10

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCM67Q709AZP10
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128K x 9 Bit Separate I/O
Synchronous Fast Static RAM
nized as 131,072 words of 9 bits. It features separate TTL input and output buff-
ers, which drive 3.3 V output levels and incorporates input and output registers
on–board with high speed SRAM. It also features transparent–write and data
pass–through capabilities.
external single clock (K). The addresses (A0 – A16), data input (D0 – D8), data
output (Q0 – Q8), write enable (W), chip enable (E), and output enable (G), are
registered in on the rising edge of clock (K).
nous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
Ball Grid Array) package.
MOTOROLA FAST SRAM
REV 2
12/23/97
Motorola, Inc. 1997
The MCM67Q709A is a 1,179,648–bit static random access memory, orga-
The synchronous design allows for precise cycle control with the use of an
The control pins (E, W, G) function differently in comparison to most synchro-
The pass–through function is always enabled. E high disables the write to the
The MCM67Q709A is available in an 86–bump surface mount PBGA (Plastic
Single 5 V
Fast Cycle Time: 10 ns Max
Single Clock Operation
TTL Input and Output Levels (Outputs LVTTL Compatible)
Address, Data Input, E, W, G Registers On–Chip
100 MHz Maximum Clock Cycle Time
Self–Timed Write
Separate Data Input and Output Pins
Transparent–Write and Pass–Through
High Output Drive Capability: 50 pF/Output at Rated Access Time
Boundary Scan Implementation
PBGA Package for High Speed Operation
5% Power Supply
G
H
A
B
C
D
E
F
J
K
V CC
V SS
V SS
A16
Q1
D7
D5
D3
1
V SS
A14
A15
A12
A13
Q7
Q5
Q3
D1
A0 – A16
E
W
G
D0 – D8
Q0 – Q8
K
SCK
SE
SDI
SDO
V CC
V SS
NC
E
2
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
MCM67Q709A
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
V SS
V SS
V SS
V SS
A10
A11
PIN ASSIGNMENT
NC
NC V SS
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
W
G
3
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
V SS V SS V SS V SS
V SS
SCK
V CC
V SS V SS V SS V SS
V SS V SS V SS V SS
V SS V SS V SS V SS
TOP VIEW
V SS
86–BUMP
4
K
PIN NAMES
V CC
V SS
V SS
V SS V SS V SS
SDI
A9
5
SDO
V SS
A8
SE
A6
6
Order this document
+ 5 V Power Supply
86 BUMP PBGA
by MCM67Q709A/D
CASE 896A–02
Scan Data Output
Scan Clock Input
V SS
MCM67Q709A
Scan Data Input
A4
A2
A5
A7
No Connection
7
Output Enable
Address Input
Not to Scale
Data Outputs
Write Enable
Scan Enable
Chip Enable
Data Inputs
Clock Input
V SS
V SS
A0
Q8
Q6
D4
D2
D0
A1
A3
8
Ground
V CC
V SS
V SS
D8
D6
Q4
Q2
Q0
9
1

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MCM67Q709AZP10 Summary of contents

Page 1

... The control pins ( function differently in comparison to most synchro- nous SRAMs. This device will not deselect with E high. The RAM remains active at all times registered high, the output pins (Q0 – Q8) will be driven registered low. The transparent write feature allows the output data to track the input data and W must be asserted to perform a transparent write (write and pass– ...

Page 2

... A12, A13, Q1, D1, Q3, D3, Q5, D5, Q7, D7, A15, A16, A14 Four added test pins. MCM67Q709A 2 BLOCK DIAGRAM MEMORY DECODERS ARRAY 128K x 9 ARRAY SENSE AMPS MUX AND WRITE 2:1 DRIVERS WRITE PULSE GENERATOR SE 1 BYPASS LS 0 SCK SH BSR OUTPUT Q0 – Q8 REGISTER SDO * L O SCK MOTOROLA FAST SRAM ...

Page 3

... V IL (min) = – 0 (min) = – 2 (pulse width ** V IH (max 0 (max 2 (pulse width CAPACITANCE (f = 1.0 MHz 3 Periodically Sampled Rather Than 100% Tested) Address and Data Input Capacitance Control Pin Input Capacitance Output Capacitance MOTOROLA FAST SRAM D0 – – Current Valid D0 – ...

Page 4

... V Figure 1a Unless Otherwise Noted MCM67Q709A–10 Unit U i Notes N Min Max 10 — — — — — ns — — — 480 Ω OUTPUT 255 Ω (b) MOTOROLA FAST SRAM ...

Page 5

... MOTOROLA FAST SRAM MCM67Q709A 5 ...

Page 6

... MCM67Q709A 6 MOTOROLA FAST SRAM ...

Page 7

... MOTOROLA FAST SRAM MCM67Q709A 7 ...

Page 8

... SCK serially shifts data through the scan registers and onto the SDO pin. To enter bypass mode simply exercise SCK with SE held low. In this mode, SDI is sampled on the rising edge of SCK. The level found on SDI is then driven out on SDO on the next falling edge of SCK. MOTOROLA FAST SRAM U i Unit N Notes ...

Page 9

... MOTOROLA FAST SRAM MCM67Q709A 9 ...

Page 10

... US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / MCM67Q709A 10 ORDERING INFORMATION (Order by Full Part Number) 67Q709A Full Part Numbers — MCM67Q709AZP10 MCM67Q709AZP10R PACKAGE DIMENSIONS ZP PACKAGE 86 PBGA CASE 896A–02 0.15 (0.006 ...

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