GE28F320C3BD70 Intel, GE28F320C3BD70 Datasheet - Page 36

• Manufacturer Part Number: GE28F320C3BD70
• Manufacturer: Intel

Specifications of GE28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

8.0
8.1
8.2
8.3
8.4
Datasheet
36
Power and Reset Specifications
Numonyx™ flash devices have a tiered approach to power savings that can significantly
reduce overall system power consumption. The Automatic Power Savings (APS) feature
reduces power consumption when the device is selected but idle. If CE# is deasserted,
the flash enters its standby mode, where current consumption is even lower. If RP# is
deasserted, the flash enter deep power-down mode for ultra-low current consumption.
The combination of these features can minimize memory power consumption, and
therefore, overall system power consumption.
Active Power (Program/Erase/Read)
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active
mode. Refer to the DC Characteristic tables for I
largest contributor to overall system power consumption. Minimizing the active current
could have a profound effect on system power consumption, especially for battery-
operated devices.
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is
read from the memory array and the address lines are idle, APS circuitry places the
device in a mode where typical current is comparable to I
static state with outputs valid until a new location is read.
Standby Power
When CE# is at a logic-high level (V
disables much of the device’s circuitry and substantially reduces power consumption.
Outputs are placed in a high-impedance state independent of the status of the OE#
signal. If CE# transitions to a logic-high level during Erase or Program operations, the
device will continue to perform the operation and consume corresponding active power
until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time
and quantify the respective power consumption in each mode for their specific
application. This approach will provide a more accurate measure of application-specific
power and energy requirements.
Deep Power-Down Mode
The deep power-down mode is activated when RP# = V
going low de-selects the memory and places the outputs in a high-impedance state.
Recovery from deep power-down requires a minimum time of t
and t
During program or erase modes, RP# transitioning low aborts the in-progress
operation. The memory contents of the address being programmed or the block being
erased are no longer valid as the data integrity has been compromised by the abort.
During deep power-down, all internal circuits are switched to a low-power savings
mode (RP# transitioning to V
Register).
PHWL
/t
PHEL
for write operations.
IL
or turning off power to the device clears the Status
IH
), the flash memory is in standby mode, which
CC
current values. Active power is the
IL
. During read modes, RP#
CCS
. The flash stays in this
PHQV
for read operations,
C3 Discrete
March 2008
290645-24