GE28F320C3BD70 Intel, GE28F320C3BD70 Datasheet - Page 43

• Manufacturer Part Number: GE28F320C3BD70
• Manufacturer: Intel

Specifications of GE28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

C3 Discrete
10.1.4.1
10.2
10.2.1
Note:
March 2008
290645-24
When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits
in the Status Register indicate whether the WSM was successful in performing the
preferred operation See
Clear Status Register
The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7, but
the WSM cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5
indicate various error conditions, these bits can be cleared only through the Clear
Status Register (0x50) command. By allowing the system software to control the
resetting of these bits, several operations may be performed (such as cumulatively
programming several addresses or erasing multiple blocks in sequence) before reading
the Status Register to determine if an error occurred during that series. Clear the
Status Register before beginning another command or sequence. The Read Array
command must be issued before data can be read from the memory array. Resetting
the device also clears the Status Register.
Program Mode
Programming is executed using a two-write cycle sequence. The Program Setup
command (0x40) is issued to the CUI, followed by a second write that specifies the
address and data to be programmed. The WSM will execute a sequence of internally
timed events to program preferred bits of the addressed location, then verify the bits
are sufficiently programmed. Programming the memory results in specific bits within an
address location being changed to a “0.” If users attempt to program “1”s, the memory
cell contents do not change and no error occurs.
The Status Register indicates programming status. While the program sequence
executes, status bit 7 is “0.” The Status Register can be polled by toggling either CE#
or OE#. While programming, the only valid commands are Read Status Register,
Program Suspend, and Program Resume.
When programming is complete, the program-status bits must be checked. If the
programming operation was unsuccessful, SR[4] is set to indicate a program failure. If
SR[3] is set, then V
the program command. If SR[1] is set, a program operation was attempted on a locked
block and the operation was aborted.
The Status Register should be cleared before attempting the next operation. Any CUI
instruction can follow after programming is completed; however, to prevent inadvertent
Status Register reads, be sure to reset the CUI to read-array mode.
12-Volt Production Programming
When V
the VCC pin.
If V
1.65 V to perform in-system flash modifications.
When V
current directly from the VPP pin. This eliminates the need for an external switching
transistor to control V
supplies can be configured for various usage models.
The 12 V V
time typically found in manufacturing processes; however, it is not intended for
extended use. You cna apply 12 V to VPP during Program and Erase operations for a
PP
is driven by a logic signal, V
PP
PP
is between 1.65 V and 3.6 V, all program and erase current is drawn through
is connected to a 12 V power supply, the device draws program and erase
PP
mode enhances programming performance during the short period of
PP
PP
was not within acceptable limits, and the WSM did not execute
.
Table 25, “Status Register Bit Definition” on page
Figure 16 on page 52
IH
min = 1.65 V. That is, V
shows examples of how the flash power
PP
must remain above
47.
Datasheet
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