GE28F320C3BD70 Intel, GE28F320C3BD70 Datasheet - Page 51

• Manufacturer Part Number: GE28F320C3BD70
• Manufacturer: Intel

Specifications of GE28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

C3 Discrete
11.5.2
Note:
11.5.3
Figure 15: Protection Register Mapping
11.6
11.6.1
March 2008
290645-24
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program
command. The 64-bit number is programmed 16 bits at a time. First, issue the
Protection Program Setup command, 0xC0. The next write to the device will latch in
address and data and program the specified location. The allowable addresses are
listed in
Register Programming Flowchart” on page
locked protection register segment will result in a Status Register error (Program Error
bit SR[4] and Lock Error bit SR[1] will be set to 1).
Do not attempt to address Protection Program commands outside the defined
protection register address space; status register can be indeterminate.
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming
bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the
Numonyx factory to protect the unique device number. This bit is set using the
Protection Program command to program 0xFFFD to the PR-LOCK location. After these
bits have been programmed, no further changes can be made to the values stored in
the protection register. Protection Program commands to a locked section will result in
a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to
1). Protection register lockout state is not reversible.
V
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range.
For fast production programming, 12 V programming can be used.
Program Protection
In addition to the flexible block locking, the V
for absolute hardware write protection of all blocks in the flash device. When V
below or equal to V
prompting the corresponding Status Register bit (SR[3]) to be set.
PP
Program and Erase Voltages
Table 22, “Device Identification Codes” on page
0x88
0x85
0x84
0x81
0x80
15 14 13 12 11 10 9
PPLK
, any Program or Erase operation will result in an error,
128-Bit Protection Register 0
(Intel Factory-Programmed)
PR Lock Register 0
(User-Programmable)
64-bit Segment
64-bit Segment
8
7
6
5
4
61. Attempting to program to a previously
3
2
PP
1
programming voltage can be held low
0
42. See
Figure 22, “Protection
PP
Datasheet
is
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