MC68HC11E0CFN3 Freescale Semiconductor, MC68HC11E0CFN3 Datasheet - Page 112

MC68HC11E0CFN3

Manufacturer Part Number
MC68HC11E0CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC11E0CFN3

Cpu Family
HC11
Device Core Size
8b
Frequency (max)
3MHz
Interface Type
SCI/SPI
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E0CFN3
Manufacturer:
MOT
Quantity:
119
Part Number:
MC68HC11E0CFN3
0
Part Number:
MC68HC11E0CFN3R2
Manufacturer:
FREESCALE
Quantity:
1 831
Serial Communications Interface (SCI)
7.7.4 Serial Communication Status Register
The SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt.
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
OR — Overrun Error Flag
NF — Noise Error Flag
112
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress).
Clear the TC flag by reading SCSR with TC set and then writing to SCDR.
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR
with IDLE set and then reading SCDR.
OR is set if a new character is received before a previously received character is read from SCDR.
Clear the OR flag by reading SCSR with OR set and then reading SCDR.
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by
reading SCSR with NF set and then reading SCDR.
0 = SCDR busy
0 = SCDR empty
0 = Transmitter busy
1 = Transmitter idle
0 = SCDR empty
1 = SCDR full
0 = RxD line active
1 = RxD line idle
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise detected
Address:
Reset:
Read:
Write:
Figure 7-6. Serial Communications Status Register (SCSR)
$102E
TDRE
Bit 7
1
= Unimplemented
TC
6
1
M68HC11E Family Data Sheet, Rev. 5.1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Freescale Semiconductor
Bit 0
0

Related parts for MC68HC11E0CFN3