SC1211STR Semtech, SC1211STR Datasheet - Page 8

• Manufacturer Part Number: SC1211STR
• Manufacturer: Semtech

Specifications of SC1211STR

• Number Of Drivers: 2
• Driver Configuration: Inverting/Non-Inverting
• Driver Type: High and Low Side
• Rise Time: 15ns
• Fall Time: 10ns
• Propagation Delay Time: 37ns
• Frequency (max): 1.5MHz
• Operating Supply Voltage (max): 15V
• Peak Output Current: 3.5A
• Power Dissipation: 2.56W
• Output Resistance: 1.5Ohm
• Operating Supply Voltage (min): 9V
• Operating Supply Voltage (typ): 12V
• Operating Temp Range: 0C to 125C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EP
• Lead Free Status / Rohs Status: Not Compliant

THEOR
THEOR
Startup and UVLO
Startup and UVLO
Gat
Gat
THEOR
THEORY OF OPERA
THEOR
The SC1211 is a high speed, Combi-Sense
put driver designed to drive top and bottom MOSFETs in
a synchronous Buck converter. It features adaptive de-
lay for shoot-through protection and VID-on-Fly opera-
tion; internal LDO for optimum gate drive voltage; and
Virtual Phase Node for Combi-Sense
drivers combined with PWM controller SC2643VX form
a multi-phase voltage regulator for advanced micropro-
cessors. A three-phase voltage regulator with 12V input
60A output is shown in the Typical Application Circuit sec-
tion.
Startup and UVLO
Startup and UVLO
Startup and UVLO
To startup the driver, a supply voltage is applied to VIN
pin of the SC1211. The top and bottom gates are held
low until VIN exceeds UVLO threshold of the driver, typi-
cally 4.0V. Then the top gate remains low and the bot-
tom gate is pulled high to turn on the bottom FET. Once
VIN exceeds UVLO threshold of the PWM controller, typi-
cally 7.5V, the soft-start begins and the PWM signal takes
fully control of the gate transitions.
Gat
Gat
Gate T
Refer to the Timing Diagrams section, the rising edge of
the PWM input initiates the bottom FET turn-off and the
top FET turn-on. After a short propagation delay (t
the bottom gate begins to fall (t
in the SC1211 monitors the bottom gate voltage to drop
below 1.4V. Then after a preset delay time (t
expired, the top gate turns on. The delay time is set to
be 20ns typically. This prevents the top FET from turning
on until the bottom FET is off. During the transition, the
inductor current is freewheeling through the body diode
of either bottom FET or top FET, upon the direction of
the inductor current. The phase node could be low
(ground) or high (VIN).
The falling edge of the PWM input controls the top FET
turn-off and the bottom FET turn-on. After a short propa-
gation delay (t
As the inductor current is commutated from the top FET
to the body diode of the bottom FET, the phase node
begins to fall. The adaptive circuit in the SC1211 de-
tects the phase node voltage. It holds the bottom FET
off until the phase node voltage has dropped below 1.0V.
This prevents the top and bottom FETs from conducting
Applications Information
POWER MANAGEMENT
2003 Semtech Corp.
e T
e T
e T
e Transition and Shoo
Y OF OPERA
Y OF OPERA
Y OF OPERATION
Y OF OPERA
ransition and Shoo
ransition and Shoo
ransition and Shoot thr
ransition and Shoo
PDL_TG
), the top gate begins to fall (t
TION
TION
TION
TION
t thr
t thr
t thr
t through Pr
F_BG
ough Pr
ough Pr
ough Pr
ough Pro o o o o t t t t t ection
). An adaptive circuit
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solution. These
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, dual out-
ection
ection
ection
ection
PDH_TG
PDL_BG
F_TG
) is
),
).
8
simultaneously or shoot-through.
Minimum Off-Time for Bottom Gate
Minimum Off-Time for Bottom Gate
Minimum Off-Time for Bottom Gate
Minimum Off-Time for Bottom Gate
Minimum Off-Time for Bottom Gate
During a load transient of the voltage regulator, the PWM
controller could generate a very narrow pulse for the
driver SC1211. The pulse is so narrow that it reaches
the rising edge threshold of the SC1211 at one point
then immediately falls below the falling edge threshold.
To response such a PWM input, the bottom gate of the
SC1211 has to pull down and pull up almost simulta-
neously, resulting in a voltage spike at the BG pin. The
spike could exceed the gate voltage rating and damage
the gate. To prevent such fast gate transition, a mini-
mum off-time (typically 75ns) for the bottom gate is de-
signed in the SC1211. When the PWM input reaches
the rising edge threshold of the SC1211, the bottom
gate pulls low and will stay low for the minimum off-time
no matter what the PWM input at the CO pin is.
VID-on-Fly Operation
VID-on-Fly Operation
VID-on-Fly Operation
VID-on-Fly Operation
VID-on-Fly Operation
Certain new processors have required to changing the
VID dynamically during the operation, or refered as VID-
on-Fly operation. A VID-on-Fly can occur under light load
or heavy load conditions. At light load, it could force the
converter to sink current. Upon turn-off of the top FET,
the reversed inductor current has to be freewheeling
through the body diode of the top FET instead of the
bottom FET. As a result, the phase node voltage remains
high. The SC1211 incorporates the ability by pulling the
bottom gate to high internally, which over rides the adap-
tive circuit and turns the bottom FET on. The delay time
from the PWM falling egde to the bottom gate turn-on is
set at 200ns typically.
Virtual Phase Node for
Virtual Phase Node for
Virtual Phase Node for
Virtual Phase Node for
Virtual Phase Node for Combi-Sense
Peak-Current-Mode control is widely employed in multi-
phase voltage regulators. It features phase current bal-
ance, fast transient response, and over current protec-
tion, etc. These are essential to low-voltage high-cur-
rent regulators designed for advanced microprocessors.
Usually, a costly current sensing resistor is required to
obtain the output inductor current information for the
peak current control. The Combi-Sense
tured by the SC1211 is an approach to sense inductor
current without using sensing resistor.
Combi-Sense
Combi-Sense
Combi-Sense
Combi-Sense
TM
www.semtech.com
SC1211
technique fea-
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