SC1211STR Semtech, SC1211STR Datasheet - Page 9

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SC1211STR

Manufacturer Part Number
SC1211STR
Description
Manufacturer
Semtech
Datasheet

Specifications of SC1211STR

Number Of Drivers
2
Driver Configuration
Inverting/Non-Inverting
Driver Type
High and Low Side
Rise Time
15ns
Fall Time
10ns
Propagation Delay Time
37ns
Frequency (max)
1.5MHz
Operating Supply Voltage (max)
15V
Peak Output Current
3.5A
Power Dissipation
2.56W
Output Resistance
1.5Ohm
Operating Supply Voltage (min)
9V
Operating Supply Voltage (typ)
12V
Operating Temp Range
0C to 125C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC EP
Lead Free Status / Rohs Status
Not Compliant

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The above circuit shows the concept of Combi-Sense
technique. An internal totem pole (Qcst, Qcsb) generates
a VPN (Virtual Phase Node) signal. This VPN follows the
DRN (or the Power Phase Node) with the same timing. A
RC network (Rcs and Ccs) is connected between VPN
and Vout. During Q1 turn-on, Qcst turns on as well. The
voltage drop across Q1 and Lo charges Ccs. During Q2
turn-on, Qcsb turns on as well. The voltage drop across
Q2 and Lo discharges Ccs. Both voltage drops are pro-
portional to the inductor current and a resistance equal
to FET’s Rdson plus ESR of the inductor. If the time con-
stant Rcs x Ccs is close to the Lo/Ro of the inductor,
where Ro is given by
the signal developed across Ccs will be proportional to
the inductor current, where Ro is the equivalent current
sensing resistance. In the above equation, Rinductor is
ESR of the inductor, Rdson_hs and Rdson_ls are the top
and bottom FET’s Rdson, and D is the duty cycle of the
converter.
Since a perfect timing match down to the nanosecond is
impossible, the VPN totem pole is held in tri-state during
the communtations of DRN in the SC1211. This avoids
errors and offset on the current detection which can be
significant since the timing mismatch is multiplied by the
input voltage. An optional capacitor between VPN and
DRN allows these two nodes to be AC coupled during
the tri-state window, hence yields a perfect timing match.
Ro
POWER MANAGEMENT
Applications Information (Cont.)
2003 Semtech Corp.
=
SC1211
R
inductor
Qcst
Qcsb
+
R
dson
VPN
PGND
VIN
Inductor C urrent Signal
_
hs
*
D
C
Rcs
+
R
DRN
dson
_
VIN
Q1
Q2
ls
*
1 (
Lo
Ccs
-
D
)
+
Vout
Co
TM
9
Refer to Semtech SC2643VX Combi-Sense
Mode Controller about the details of the Combi-Sense
technique.
Optimized Gat
Optimized Gat
Optimized Gat
Optimized Gat
Optimized Gate Driv
With the supply voltage in between 9V to 16V, an inter-
nal LDO is designed with the SC1211 to bring the volt-
age to a lower level for gate drive. An external Ceramic
capacitor(1uF to 4.7uF) connected in between Vreg to
ground is needed to support the LDO. The LDO output is
connected to low gate drive internally, and has to be
connected to high gate drive through an external boot-
strap circuit. The LDO output voltage is set at 8.5V. The
manufacture data and bench tested results show that,
for low R
mum gate drive voltage is around 8.5V, where the total
power losses of power FETs, including conduction loss
and switching loss, are minimized.
Thermal Shut Down
Thermal Shut Down
Thermal Shut Down
Thermal Shut Down
Thermal Shut Down
The SC1211 will shut down by pulling both driver out-
puts low if its junction temperature, T
COMPONENT SELECTION
COMPONENT SELECTION
COMPONENT SELECTION
COMPONENT SELECTION
COMPONENT SELECTION
Switching F
Switching F
Switching Freq
Switching F
Switching F
The SC1211 is capable of providing up to 3.5A peak
drive current, and operating up to 1.5MHz PWM frequency
without causing thermal stress on the driver. The selec-
tion of switching frequency, together with inductor and
FETs is a trade-off between the cost, size, and thermal
management of a multi-phase voltage regulator. In mod-
ern microprocessor applications, these parameters could
be in the range of:
Switching Frequency 100kHz to 500kHz per phase
Inductor Value
FETs
Bootstrap Circuit
Bootstrap Circuit
Bootstrap Circuit
Bootstrap Circuit
Bootstrap Circuit
The SC1211 uses an external bootstrap circuit to pro-
vide a voltage for the top FET drive. This voltage, refer-
ring to the Phase Node, is held up by a bootstrap capaci-
dson
req
req
requency
req
FETs run at applied load current, the opti-
e Driv
e Driv
e Driv
e Drive V
uency
uency
uency, Induct
uency
0.2uH to 2uH
4m-ohm to 20m-ohm R
20nC to 100nC total gate charge
e V
e V
e V
e Voltage
, Induct
, Induct
, Inductor and MOSFET
, Induct
oltage
oltage
oltage
oltage
or and MOSFET
or and MOSFET
or and MOSFETs s s s s
or and MOSFET
j
, exceeds 155°C.
www.semtech.com
SC1211
TM
dson
Current

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