UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet
UPD78F0078GK-9ET-A
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UPD78F0078GK-9ET-A Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual PD780078, 780078Y Subseries 8-Bit Single-Chip Microcontrollers PD780076 PD780078 PD78F0078 PD780076Y PD780078Y PD78F0078Y Document No. U14260EJ4V0UD00 (4th edition) Date Published February 2006 N CP(K) 2000, 2003 Printed in Japan ...
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User’s Manual U14260EJ4V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM, FIP, and IEBus are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 ...
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The information in this document is current as of September, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date ...
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User’s Manual U14260EJ4V0UD ...
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Readers This manual is intended for user engineers who wish to understand the functions of the PD780078, 780078Y Subseries and design and develop application systems and programs for these devices. PD780078 Subseries: PD780078Y Subseries: Purpose This manual is intended to ...
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Differences Between PD780078 and 780078Y Subseries The configuration of the serial interface differs in PD780078 and 780078Y Subseries products. Subseries Item Configuration of UART0 serial interface UART2/SIO3 CSI1 IIC0 Chapter Organization This manual divides the descriptions for the subseries into ...
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Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Binary Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices PD780078, 780078Y Subseries ...
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Documents Related to Flash Memory Programming PG-FP3 Flash Memory Programmer User’s Manual PG-FP4 Flash Memory Programmer User’s Manual Other Documents SEMICONDUCTOR SELECTION GUIDE – Products and Packages – Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) ........................................................................ 1.1 Expanded-Specification Products and Conventional Products ...................................... 1.2 Features ................................................................................................................................ 1.3 Applications ......................................................................................................................... 1.4 Ordering Information ........................................................................................................... 1.5 Pin Configuration (Top View) .............................................................................................. 1.6 78K/0 Series Lineup ............................................................................................................. 1.7 Block Diagram ...................................................................................................................... 1.8 ...
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IC (mask ROM version only) ..................................................................................................... 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ................................... CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) ......................................................... 4.1 Pin Function List .................................................................................................................. 4.2 Description of Pin Functions .............................................................................................. 4.2.1 P00 to ...
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Short direct addressing ............................................................................................................. 5.4.5 Special function register (SFR) addressing ............................................................................... 5.4.6 Register indirect addressing ...................................................................................................... 5.4.7 Based addressing ..................................................................................................................... 5.4.8 Based indexed addressing ........................................................................................................ 5.4.9 Stack addressing ....................................................................................................................... CHAPTER 6 PORT FUNCTIONS ..................................................................................................... 6.1 Port Functions ...................................................................................................................... 6.2 ...
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Registers to Control 16-Bit Timer/Event Counters 00, 01 ................................................ 148 8.4 Operation of 16-Bit Timer/Event Counters 00, 01 ............................................................. 158 8.4.1 Interval timer operation ............................................................................................................. 8.4.2 External event counter operation .............................................................................................. 8.4.3 Pulse width measurement operations ....................................................................................... 8.4.4 Square-wave ...
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Watchdog timer operation ......................................................................................................... 11.4.2 Interval timer operation ............................................................................................................. CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ........................................... 220 12.1 Clock Output/Buzzer Output Controller Functions .......................................................... 220 12.2 Configuration of Clock Output/Buzzer Output Controller ................................................ 221 12.3 Registers to Control Clock ...
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Configuration of Serial Interface SIO3 ............................................................................... 311 16.3 Registers to Control Serial Interface SIO3 ........................................................................ 311 16.4 Operation of Serial Interface SIO3 ...................................................................................... 314 16.4.1 Operation stop mode ................................................................................................................. 16.4.2 3-wire serial I/O mode ............................................................................................................... CHAPTER 17 SERIAL INTERFACE ...
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Maskable interrupt request acknowledgment operation ............................................................ 19.4.3 Software interrupt request acknowledgment operation ............................................................. 19.4.4 Multiple interrupt servicing ........................................................................................................ 19.4.5 Interrupt request hold ................................................................................................................ CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION ..................................................... 417 20.1 External Device Expansion Function ................................................................................. 417 20.2 ...
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS) ..................... 528 CHAPTER 28 PACKAGE DRAWINGS .............................................................................................. 557 CHAPTER 29 RECOMMENDED SOLDERING CONDITIONS ......................................................... 560 APPENDIX A DIFFERENCES BETWEEN PD78018F, 780024A, 780034A, AND 780078 SUBSERIES .......................................................................................... 563 APPENDIX B DEVELOPMENT TOOLS .......................................................................................... 566 B.1 ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) 1.1 Expanded-Specification Products and Conventional Products The expanded-specification products and conventional products refer to the following products. Expanded-specification products: Products with a rank Conventional products: Note The rank is indicated by the 5th digit ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) 1.2 Features • Minimum instruction execution time changeable from high speed (expanded-specification products 0.166 MHz operation with main system clock, conventional products 0.238 s: @ 8.38 MHz operation with main system ...
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Applications Personal computers, air conditioners, dashboards, car audio, etc. <R> 1.4 Ordering Information Part Number PD780076GC- -8BS PD780076GC- -8BS-A PD780076GC- -AB8 PD780076GC- -AB8-A PD780076GK- -9ET PD780076GK- -9ET-A PD780078GC- -8BS PD780078GC- -8BS-A PD780078GC- -AB8 PD780078GC- -AB8-A PD780078GK- -9ET PD780078GK- -9ET-A ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) 1.5 Pin Configuration (Top View) • 64-pin plastic LQFP (14 14) • 64-pin plastic QFP (14 14) • 64-pin plastic TQFP (12 12 ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES A15: Address bus AD0 to AD7: Address/data bus ADTRG: AD trigger input ANI0 to ANI7: Analog input ASCK0, ASCK2: Asynchronous serial clock ASTB: Address strobe AV : Analog reference voltage REF AV ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) 1.6 78K/0 Series Lineup The 78K/0 Series product lineup is illustrated below. Part numbers in the boxes indicate subseries names. Products in mass production Control PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 100-pin PD780058 80-pin ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) The major functional differences between the subseries are shown below. • Subseries without the suffix Y Function ROM Subseries Name Capacity 8-Bit 16-Bit Watch WDT A/D Control PD78075B ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) 1.7 Block Diagram TI000/TO00/P70 16-bit timer/ event counter 00 TI010/P71 TI001/TO01/P75 16-bit timer/ event counter 01 TI011/P74 8-bit timer/ TI50/TO50/P72 event counter 50 8-bit timer/ TI51/TO51/P73 event counter 51 Watch timer Watchdog timer RxD0/P23 ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) 1.8 Outline of Functions Part Number Item Internal memory ROM High-speed RAM Expansion RAM Memory space General-purpose registers Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction set I/O ...
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CHAPTER 1 OUTLINE ( PD780078 SUBSERIES) The following table outlines the timer/event counters (for details, refer to CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01, CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51, CHAPTER 10 WATCH TIMER, and CHAPTER 11 WATCHDOG TIMER). ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) 2.1 Expanded-Specification Products and Conventional Products The expanded-specification products and conventional products refer to the following products. Expanded-specification products: Products with a rank Conventional products: Note The rank is indicated by the 5th digit ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) 2.2 Features • Minimum instruction execution time changeable from high speed (0.238 s: @ 8.38 MHz operation with main system clock) to ultra-low speed (122 s: @ 32.768 kHz operation with subsystem clock) • ...
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Applications Personal computers, air conditioners, dashboards, car audio, etc. <R> 2.4 Ordering Information Part Number PD780076YGC- -8BS PD780076YGC- -8BS-A PD780076YGC- -AB8 PD780076YGC- -AB8-A PD780076YGK- -9ET PD780076YGK- -9ET-A PD780078YGC- -8BS PD780078YGC- -8BS-A PD780078YGC- -AB8 PD780078YGC- -AB8-A PD780078YGK- -9ET PD780078YGK- -9ET-A ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) 2.5 Pin Configuration (Top View) • 64-pin plastic LQFP (14 14) • 64-pin plastic QFP (14 14) • 64-pin plastic TQFP (12 12 ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES A15: Address bus AD0 to AD7: Address/data bus ADTRG: AD trigger input ANI0 to ANI7: Analog input ASCK0, ASCK2: Asynchronous serial clock ASTB: Address strobe AV : Analog reference voltage REF AV ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) 2.6 78K/0 Series Lineup The 78K/0 Series product lineup is illustrated below. Part numbers in the boxes indicate subseries names. Products in mass production Control PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 100-pin PD780058 80-pin ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) The major functional differences between the subseries are shown below. • Subseries with the suffix Y Function ROM Subseries Name Capacity 8-Bit 16-Bit Watch WDT A/D Control PD78078Y ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) 2.7 Block Diagram TI000/TO00/P70 16-bit timer/ TI010/P71 event counter 00 TI001/TO01/P75 16-bit timer/ event counter 01 TI011/P74 8-bit timer/ TI50/TO50/P72 event counter 50 8-bit timer/ TI51/TO51/P73 event counter 51 Watch timer Watchdog timer RxD0/P23 ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) 2.8 Outline of Functions Part Number Item Internal memory ROM High-speed RAM Expansion RAM Memory space General-purpose registers Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction set I/O ...
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CHAPTER 2 OUTLINE ( PD780078Y SUBSERIES) The following table outlines the timer/event counters (for details, refer to CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01, CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51, CHAPTER 10 WATCH TIMER, and CHAPTER 11 WATCHDOG TIMER). ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) 3.1 Pin Function List (1) Port pins (1/2) Pin Name I/O P00 I/O Port 0 4-bit I/O port P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) (1) Port pins (2/2) Pin Name I/O P70 I/O Port 7 6-bit I/O port P71 Input/output mode can be specified in 1-bit units. P72 An on-chip pull-up resistor can be used by setting ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) (2) Non-port pins (2/2) Pin Name I/O TI011 Input Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 TI50 External count clock input to 8-bit timer/event counter 50 TI51 External ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P03 (Port 0) P00 to P03 function as a 4-bit I/O port. Besides serving as an I/O port, they also function as external interrupt inputs ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) (2) Control mode These pins function as data I/O and clock I/O for serial interfaces CSI1 and UART0. (a) SI1 Serial data input pin for serial interface CSI1. (b) SO1 Serial data output ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) ( Serial data output pin for serial interface UART2. (f) ASCK2 Serial clock input pin for serial interface UART2. 3.2.5 P40 to P47 (Port 4) P40 to P47 function as ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) 3.2.8 P70 to P75 (Port 7) P70 to P75 function as a 6-bit I/O port. Besides serving as an I/O port, they also function as timer I/O, clock output, and buzzer output. The ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) 3.2.9 P80 (Port 8) P80 is a 1-bit I/O port. Besides serving as an I/O port, it also functions as the chip select input of serial interface CSI1. The following operating modes can ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) When there is a potential difference between the V two pins is too long or external noise is input to the V 3.2.18 IC (mask ROM version only) The IC (internally connected) pin ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 3-1 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 3-1 for the configuration ...
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Pin Name P50/A8 to P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI000/TO00 P71/TI010 P72/TI50/TO50 P73/TI51/TO51 P74/TI011/PCL P75/TI001/TO01/BUZ P80/SS1 <R> RESET XT1 XT2 AV REF (for mask ROM version (for flash memory version) CHAPTER 3 PIN FUNCTIONS ( ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-H Pull-up enable V DD0 Data P-ch Output N-ch disable V SS0 Input enable Type 8-C Pull-up enable V DD0 Data P-ch Output N-ch ...
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CHAPTER 3 PIN FUNCTIONS ( PD780078 SUBSERIES) Type 13-S Mask option Data N-ch Output disable V SS0 Type 16 Feedback cut-off P-ch XT1 XT2 Figure 3-1. Pin I/O Circuits (2/2) Type 25 V DD0 IN/OUT Comparator Input enable User’s Manual ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) 4.1 Pin Function List (1) Port pins (1/2) Pin Name I/O P00 I/O Port 0 4-bit I/O port P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) (1) Port pins (2/2) Pin Name I/O P70 I/O Port 7 6-bit I/O port P71 Input/output mode can be specified in 1-bit units. P72 An on-chip pull-up resistor can be used by setting ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) (2) Non-port pins (2/2) Pin Name I/O TI001 Input External count clock input to 16-bit timer/event counter 01. Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 TI011 Capture ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P03 (Port 0) P00 to P03 function as a 4-bit I/O port. Besides serving as an I/O port, they also function as external interrupt inputs ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) (2) Control mode These pins function as data I/O and clock I/O for serial interfaces CSI1 and UART0. (a) SI1 Serial data input pin for serial interface CSI1. (b) SO1 Serial data output ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) ( Serial data output pin for serial interface UART2. (f) ASCK2 Serial clock input pin for serial interface UART2. 4.2.5 P40 to P47 (Port 4) P40 to P47 function as ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) 4.2.8 P70 to P75 (Port 7) P70 to P75 function as a 6-bit I/O port. Besides serving as an I/O port, they also function as timer I/O, clock output, and buzzer output. The ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) 4.2.9 P80 (Port 8) P80 is a 1-bit I/O port. Besides serving as an I/O port, it also functions as the chip select input of serial interface CSI1. The following operating modes can ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) When there is a potential difference between the V two pins is too long or external noise is input to the V 4.2.18 IC (mask ROM version only) The IC (internally connected) pin ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) 4.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 4-1 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 4-1 for the configuration ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) Pin Name P50/A8 to P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI000/TO00 P71/TI010 P72/TI50/TO50 P73/TI51/TO51 P74/TI011/PCL P75/TI001/TO01/BUZ P80/SS1 <R> RESET XT1 XT2 AV REF (for mask ROM version (for flash ...
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CHAPTER 4 PIN FUNCTIONS ( PD780078Y SUBSERIES) Figure 4-1. Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-H V Pull-up enable V DD0 Data P-ch Output N-ch disable V SS0 Input enable Type 8-C V Pull-up ...
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CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces Products in the PD780078, 780078Y Subseries can each access memory space. Figures 5-1 to 5-3 show the memory maps. Caution The initial value of the memory size switching register (IMS) ...
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Figure 5-2. Memory Map ( PD780078, 780078Y) FFFFH FF00H FEFFH General-purpose FEE0H FEDFH Internal high-speed RAM FB00H FAFFH F7FFH Internal expansion RAM Data memory space F3FFH F000H EFFFH ROM/RAM space ...
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Figure 5-3. Memory Map ( PD78F0078, 78F0078Y) FFFFH FF00H FEFFH General-purpose FEE0H FEDFH Internal high-speed RAM FB00H FAFFH F7FFH Data memory space F3FFH F000H EFFFH ROM/RAM space in which instructions ...
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Internal program memory space The internal program memory space contains the program and table data. Normally addressed with the program counter (PC). The PD780078, 780078Y Subseries incorporate internal ROM (mask ROM or flash memory), as listed below. ...
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Internal data memory space The PD780078, 780078Y Subseries incorporate the following on-chip high-speed RAMs. (1) Internal high-speed RAM The 1024-byte area FB00H to FEFFH is allocated to the internal high-speed RAM. The 32-byte area FEE0H to FEFFH is allocated ...
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Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...
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Figure 5-5. Correspondence Between Data Memory and Addressing ( PD780078, 780078Y) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH ...
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CHAPTER 5 CPU ARCHITECTURE Figure 5-6. Correspondence Between Data Memory and Addressing ( PD78F0078, 78F0078Y) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits ...
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Processor Registers The PD780078, 780078Y Subseries incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) ...
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Interrupt enable flag (IE) This flag controls the interrupt request acknowledgment operations of the CPU. When the interrupt disabled (DI) state is set, and only non-maskable interrupt requests become acknowledgeable. Other interrupt requests are all disabled. ...
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SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. ...
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Figure 5-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP is FEDEH (b) RET instruction (when SP is FEDEH (c) RETI, RETB instructions (when SP is FEDDH) SP FEE0H SP FEDDH ...
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Figure 5-12. General-Purpose Register Configuration FEFFH BANK0 FEF8H BANK1 FEF0H BANK2 FEE8H BANK3 FEE0H FEFFH BANK0 FEF8H BANK1 FEF0H BANK2 FEE8H BANK3 FEE0H 76 CHAPTER 5 CPU ARCHITECTURE (a) Absolute name 16-bit processing RP3 RP2 RP1 RP0 15 0 (b) ...
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Special function registers (SFR) Unlike a general-purpose register, each special function register has a special function. They are allocated in the area FF00H to FFFFH. The special function registers can be manipulated like the general-purpose registers, with operation, transfer ...
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Table 5-3. Special Function Register List (1/3) Address Special Function Register (SFR) Name FF00H Port register 0 FF01H Port register 1 FF02H Port register 2 FF03H Port register 3 FF04H Port register 4 FF05H Port register 5 FF06H Port register ...
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Table 5-3. Special Function Register List (2/3) Address Special Function Register (SFR) Name FF30H Pull-up resistor option register 0 FF32H Pull-up resistor option register 2 FF33H Pull-up resistor option register 3 FF34H Pull-up resistor option register 4 FF35H Pull-up resistor ...
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Table 5-3. Special Function Register List (3/3) Address Special Function Register (SFR) Name FF94H Asynchronous serial interface status register 2 FF95H Asynchronous serial interface transmit status register 2 FFA0H Asynchronous serial interface mode register 0 FFA1H Asynchronous serial interface status ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A, AX) in the general-purpose register area ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register specify code (Rn and RPn instruction word in the registered bank specified by the register bank select flags (RBS0 and ...
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Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] 7 addr16 (lower) ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function ...
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Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified by the register bank select flags (RBS0 and RBS1) serve as an operand address for addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified by the register bank select flags ...
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Based indexed addressing [Function] The register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified by ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The PD780078, 780078Y Subseries incorporate eight input ports and 44 I/O ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied ...
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Table 6-1. Port Functions ( PD780078 Subseries) Pin Name P00 Port 0 4-bit I/O port. P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can be used by setting software. P03 P10 to P17 Port ...
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Table 6-2. Port Functions ( PD780078Y Subseries) Pin Name P00 Port 0 4-bit I/O port. P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can be used by setting software. P03 P10 to P17 Port ...
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Port Configuration A port consists of the following hardware. Item Control registers Ports Pull-up resistor Note Two for the PD780078Y Subseries. 6.2.1 Port 0 Port 4-bit I/O port with an output latch. Port 0 can be ...
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Figure 6-2. Block Diagram of P00 to P03 WR PU PU0 PU00 to PU03 Alternate function RD WR PORT Output latch (P00 to P03 PM0 PM00 to PM03 PU0: Pull-up resistor option register 0 PM0: Port mode register ...
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Port 1 Port 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 6-3 shows a block diagram of port 1. Figure 6-3. Block Diagram of P10 to P17 RD RD: ...
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Port 2 Port 6-bit I/O port with an output latch. Port 2 can be set to the input or output mode in 1-bit units using port mode register 2 (PM2). An on-chip pull-up resistor can be ...
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CHAPTER 6 PORT FUNCTIONS Figure 6-5. Block Diagram of P21 WR PU PU2 PU21 RD WR PORT Output latch (P21 PM2 PM21 Alternate function SS1 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read ...
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WR PU PU2 PU22 Alternate function RD WR PORT Output latch (P22 PM2 PM22 Alternate function PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal WR : Write signal 102 CHAPTER 6 PORT ...
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CHAPTER 6 PORT FUNCTIONS Figure 6-7. Block Diagram of P24 WR PU PU2 PU24 RD WR PORT Output latch (P24 PM2 PM24 Alternate function PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal ...
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Port 3 ( PD780078 Subseries) Port 7-bit I/O port with an output latch. Port 3 can be set to the input or output mode in 1-bit units using port mode register 3 (PM3). This port has ...
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CHAPTER 6 PORT FUNCTIONS Figure 6-9. Block Diagram of P32 and P33 ( PD780078 Subseries PORT Output latch (P32, P33 PM3 PM32, PM33 PM3: Port mode register 3 RD: Read signal WR : Write signal User’s ...
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Figure 6-10. Block Diagram of P34 to P36 ( PD780078 Subseries PU3 PU34 to PU36 Alternate function RD WR PORT Output latch (P34 to P36 PM3 PM34 to PM36 Alternate function PU3: Pull-up resistor option register ...
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Port 3 ( PD780078Y Subseries) Port 7-bit I/O port with an output latch. Port 3 can be set to the input or output mode in 1-bit units using port mode register 3 (PM3). This port has ...
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Figure 6-12. Block Diagram of P32 and P33 ( PD780078Y Subseries PORT Output latch (P32, P33 PM3 PM32, PM33 Alternate function PM3: Port mode register 3 RD: Read signal WR : Write signal 108 CHAPTER 6 ...
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CHAPTER 6 PORT FUNCTIONS Figure 6-13. Block Diagram of P34 to P36 ( PD780078Y Subseries PU3 PU34 to PU36 Alternate function RD WR PORT Output latch (P34 to P36 PM3 PM34 to PM36 Alternate function PU3: ...
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Port 4 Port 8-bit I/O port with an output latch. Port 4 can be set to the input or output mode in 1-bit units using port mode register 4 (PM4). An on-chip pull-up resistor can be ...
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CHAPTER 6 PORT FUNCTIONS Figure 6-15. Block Diagram of Falling Edge Detector P40 P41 P42 P43 P44 P45 P46 P47 1 when MEM = 01H User’s Manual U14260EJ4V0UD Falling edge detector INTKR 111 ...
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Port 5 Port 8-bit I/O port with an output latch. Port 5 can be set to the input or output mode in 1-bit units using port mode register 5 (PM5). An on-chip pull-up resistor can be ...
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Port 6 Port 4-bit I/O port with an output latch. Port 6 can be set to the input or output mode in 1-bit units using port mode register 6 (PM6). An on-chip pull-up resistor can be ...
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WR PU PU6 PU66 RD WR PORT Output latch (P66 PM6 PM66 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 RD: Read signal WR : Write signal 114 CHAPTER 6 PORT FUNCTIONS Figure 6-18. Block ...
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Port 7 Port 6-bit I/O port with an output latch. Port 7 can be set to the input or output mode in 1-bit units using port mode register 7 (PM7). An on-chip pull-up resistor can be ...
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WR PU PU7 PU71 Alternate function RD WR PORT Output latch (P71 PM7 PM71 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR : Write signal 116 CHAPTER 6 PORT FUNCTIONS Figure ...
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Port 8 Port 1-bit I/O port with an output latch. Port 8 can be set to the input or output mode in 1-bit units using port mode register 8 (PM8). An on-chip pull-up resistor can be ...
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Port Function Control Registers The following three types of registers control the ports. • Port mode registers (PM0, PM2 to PM8) • Port registers (P0 to P8) • Pull-up resistor option registers (PU0, PU2 to PU8) (1) Port mode ...
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CHAPTER 6 PORT FUNCTIONS Figure 6-22. Format of Port Mode Register (PM0, PM2 to PM8) Address: FF20H After reset: FFH R/W Symbol 7 6 PM0 1 1 Address: FF22H After reset: FFH R/W Symbol 7 6 PM2 1 1 Address: ...
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Table 6-6. Port Mode Registers and Output Latch Settings When Alternate Function Is Used (1/2) Pin Name P00 to P02 INTP0 to INTP2 P03 INTP3 ADTRG P10 to P17 ANI0 to ANI7 P20 SI1 P21 SO1 P22 SCK1 P23 RxD0 ...
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Table 6-6. Port Mode Registers and Output Latch Settings When Alternate Function Is Used (2/2) Pin Name P70 TI000 TO00 P71 TI010 P72 TI50 TO50 P73 TI51 TO51 P74 TI011 PCL P75 TI001 TO01 BUZ P80 SS1 Remark : Don’t ...
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Port registers (P0 to P8) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read ...
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Pull-up resistor option registers (PU0, PU2 to PU8) These registers are used to set whether to connect an on-chip pull-up resistor at each port or not. By setting PU0 and PU2 to PU8, the on-chip pull-up resistors of the ...
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Figure 6-24. Format of Pull-Up Resistor Option Register (PU0, PU2 to PU8) Address: FF30H After reset: 00H Symbol 7 6 PU0 0 0 Address: FF32H After reset: 00H Symbol 7 6 PU2 0 0 Address: FF33H After reset: 00H Symbol ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed in ...
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Selection of Mask Option The following mask option is provided in the mask ROM versions. The flash memory versions have no mask options. Table 6-7. Comparison Between Mask ROM Version and Flash Memory Version Pin Name Note Mask option ...
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CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates a ...
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Figure 7-1. Block Diagram of Clock Generator FRC Subsystem XT1 f XT clock oscillator XT2 Main system X1 clock f X2 oscillator X STOP 128 CHAPTER 7 CLOCK GENERATOR Internal bus Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 ...
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Clock Generator Control Registers The clock generator is controlled by the following two registers. • Processor clock control register (PCC) • Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) PCC selects the CPU clock and ...
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Figure 7-2. Format of Processor Clock Control Register (PCC) Address: FFFBH After reset: 04H Symbol 7 6 PCC MCC FRC MCC 0 Oscillation possible 1 Oscillation stopped FRC 0 Internal feedback resistor used 1 Internal feedback resistor not used CLS ...
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The fastest instructions of the PD780078 and 780078Y Subseries are carried out in two CPU clocks. The relationship between the CPU clock (f Table 7-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (f CPU f X ...
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Oscillation stabilization time select register (OSTS) This register is used to select the oscillation stabilization time from when reset is effected or STOP mode is released to when oscillation is stabilized. OSTS is set by an 8-bit memory manipulation ...
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System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (8.38 MHz TYP.) connected to the X1 and X2 pins. External clocks can be input to the ...
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Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (32.768 kHz TYP.) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal ...
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CHAPTER 7 CLOCK GENERATOR Caution 1. When using the main system clock oscillator and subsystem clock oscillator, wire as follows in the area enclosed by broken lines in Figures 7-4 and 7-5 to avoid an adverse effect from wiring capacitance. ...
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Figure 7-6. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high fluctuating current (e) Signals are fetched SS1 Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. ...
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When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. XT1: Connect directly ...
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Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock f CPU • ...
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Main system clock operations When operating with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation-guaranteed instruction ...
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Subsystem clock operations When operating with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 s ...
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System clock and CPU clock switching procedure This section describes procedure for switching between the system clock and CPU clock. Figure 7-9. System Clock and CPU Clock Switching V DD RESET Interrupt request signal System clock CPU clock <1> ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.1 Functions of 16-Bit Timer/Event Counters 00, 01 16-bit timer/event counters 00, 01 have the following functions. (1) Interval timer 16-bit timer/event counters 00, 01 generate interrupt requests at the preset time interval. ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.2 Configuration of 16-Bit Timer/Event Counters 00, 01 16-bit timer/event counters 00, 01 consist of the following hardware. Table 8-1. Configuration of 16-Bit Timer/Event Counters 00, 01 Item Timer counter Register Timer input ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-2. Block Diagram of 16-Bit Timer/Event Counter 01 Internal bus Capture/compare control register 01 (CRC01) CRC021 CRC011 CRC001 To CR011 Noise 16-bit timer capture/compare elimi- TI011/PCL/P74 register 001 (CR001) nator f /2 ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Table 8-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC01n = 1, CRC00n = 1) CR00n Capture Trigger Falling edge ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.3 Registers to Control 16-Bit Timer/Event Counters 00, 01 The following six types of registers are used to control 16-bit timer/event counters 00, 01. • 16-bit timer mode control register 0n (TMC0n) • ...
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Figure 8-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H Symbol 7 6 TMC00 0 0 <R> TMC003 TMC002 OVF00 0 Overflow not detected 1 Overflow ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FF64H After reset: 00H Symbol TMC01 Operating mode <R> TMC013 TMC012 and clear mode selection ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (2) Capture/compare control register 0n (CRC0n This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n). CRC0n is set by a 1-bit or 8-bit memory manipulation ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-9. Format of Capture/Compare Control Register 01 (CRC01) Address: FF66H After reset: 00H Symbol 7 6 CRC01 0 0 CRC021 0 Operate as compare register 1 Operate as capture register CRC011 0 ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (3) 16-bit timer output control register 0n (TOC0n This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/ reset, output inversion ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-11. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FF67H After reset: 00H Symbol 7 6 TOC01 0 0 TOC041 0 Inversion operation disabled 1 Inversion operation enabled LVS01 LVR01 ...
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Prescaler mode register 0n (PRM0n This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI00n, TI01n pin input valid edges. PRM0n is set by an 8-bit memory manipulation instruction. ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-13. Format of Prescaler Mode Register 01 (PRM01) Address: FF65H After reset: 00H Symbol 7 PRM01 ES111 ES101 ES111 ES101 ES011 ES001 PRM011 PRM001 ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (5) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P70/TO00/TI000 and P75/TO01/TI001/BUZ pins for timer output, set PM70 and PM75, and the output latches ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.4 Operation of 16-Bit Timer/Event Counters 00, 01 8.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 8-15 allows operation ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-16. Interval Timer Configuration Diagram Note / Note Note ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 When the compare register is changed during timer count operation, if the value after 16-bit timer capture/ compare register 00n (CR00n) is changed is smaller than that of 16-bit timer counter 0n (TM0n), ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.4.2 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 8-19 for the set value). <2> Set the count clock by using ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-20. External Event Counter Configuration Diagram Noise eliminator X Valid edge of TI00n Note OVF0n is 1 only when 16-bit timer capture/compare register 00n is set to FFFFH. Figure ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are two ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) is ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-24. Configuration Diagram for Pulse Width Measurement with Free-Running Counter Note Note Note ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode possible to simultaneously measure the pulse widths of the two signals ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-27. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock 0000H 0001H TM0n count value TI00n pin input CR01n capture value INTTM01n TI01n pin input ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode possible to measure the pulse width of the signal ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-29. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM0n count value 0000H 0001H TI00n pin input CR01n capture value ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-30. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0n (TMC0n TMC0n (b) Capture/compare control ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 8-32 for the ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-32. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n TOC04n LVS0n TOC0n 0/1 (d) Prescaler mode register ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.4.5 PPG output operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 8-34 allows operation as PPG (Programmable Pulse Generator) output. Setting The ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-34. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n TMC0n3 TMC0n (b) Capture/compare control register 0n ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-35. PPG Output Configuration Diagram Note Note Note Note ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.5 Program List Caution The following sample program is shown as an example to describe the operation of semiconductor products and their applications. information to your devices, design the devices after performing evaluation ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.5.1 Interval timer /*******************************************************************************/ /* /* Setting example of timer 00 interval timer mode /* Cycle set to 130 as intervalTM00 (at 8.38 MHz for 1 ms) /* Variable ppgdata prepared as rewrite ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.5.2 Pulse width measurement by free-running counter and one capture register /******************************************************************************/ /* /* Timer 00 operation sample /* Pulse width measurement example by free-running and CR010 /* Measurement results ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.5.3 Two pulse widths measurement by free-running counter /******************************************************************************/ /* /* Timer 00 operation sample /* Two-pulse-width measurement sample by free-running /* Measurement results bits and not checked ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00 INTTM000 interrupt function */ void intervalint() { unsigned int work; /******************************************************/ /* /* Define variables required for interrupt here /* /******************************************************/ work = CR000; data[4] = work - data[5]; data[5] = work; ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.5.4 Pulse width measurement by restart /**************************************************************************/ /* /* Timer 00 operation sample /* Pulse width measurement example by restart /* Measurement results bits, not to be checked for errors ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.5.5 PPG output /******************************************************************************/ /* /* Timer 00 PPG mode setting example /* Cycle set to 130 as intervalTM00 /* Active period set active_time /* Array ppgdata prepared as data ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 8.6 Cautions for 16-Bit Timer/Event Counters 00, 01 (1) Timer start errors An error one clock may occur in the time required for a match signal to be generated after ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (5) Operation of OVF0n flag <1> The OVF0n flag is also set the following case. Either of the clear & start mode entered on a match between TM0n and CR00n, ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 Figure 8-39. Capture Register Data Retention Timing Count clock TM0n count value Edge input INTTM01n Capture read signal CR01n capture value X (7) Timer operation <1> Even if 16-bit timer counter 0n (TM0n) ...
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CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01 (10) Edge detection <1> If the TI00n pin or the TI01n pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 9.1 Functions of 8-Bit Timer/Event Counters 50, 51 8-bit timer/event counters 50, 51 (TM50, TM51) have the following two modes. (1) Mode using 8-bit timer/event counters 50, 51 alone (discrete mode) The timer ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 50 8-bit timer compare register 50 (CR50) Note 1 TI50/TO50/P72 8-bit timer ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 9.2 Configuration of 8-Bit Timer/Event Counters 50, 51 8-bit timer/event counters 50, 51 consist of the following hardware. Table 9-1. Configuration of 8-Bit Timer/Event Counters 50, 51 Item Timer counter Register Timer input ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 (2) 8-bit timer compare register 5n (CR5n When CR5n is used as a compare register in other than PWM mode, the value set in CR5n is constantly compared with ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 9.3 Registers to Control 8-Bit Timer/Event Counters 50, 51 The following four types of registers are used to control 8-bit timer/event counters 50, 51. • Timer clock select register 5n (TCL5n) • 8-bit ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 9-6. Format of Timer Clock Select Register 51 (TCL51) Address: FF79H After reset: 00H Symbol 7 6 TCL51 0 0 TCL512 TCL511 ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 9-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF70H After reset: 00H R/W Symbol 7 6 TMC50 TCE50 TMC506 TCE50 0 After clearing to 0, count operation disabled (prescaler ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 9-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF78H After reset: 00H Symbol 7 6 TMC51 TCE51 TMC516 TCE51 0 After clearing to 0, count operation disabled (prescaler disabled) ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 (3) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P72/TO50/TI50 and P73/TI51/TO51 pins for timer output, set PM72 and PM73, and the output latches ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 9.4 Operation of 8-Bit Timer/Event Counters 50, 51 9.4.1 8-bit interval timer operation The 8-bit timer/event counters operate as interval timers that generate interrupt requests repeatedly at intervals of the count value preset ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 9-10. Interval Timer Operation Timing (2/3) Count clock TM5n 00H CR5n TCE5n INTTM5n t Count clock TM5n 01H CR5n FFH TCE5n INTTM5n Remark (b) When CR5n = 00H ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 9-10. Interval Timer Operation Timing (3/3) (d) Operated by CR5n transition (M < N) Count clock TM5n N 00H CR5n TCE5n H INTTM5n (e) Operated by CR5n transition (M > N) Count ...