TC58DVM82A1FT00

Manufacturer Part NumberTC58DVM82A1FT00
ManufacturerToshiba
TC58DVM82A1FT00 datasheet
 


Specifications of TC58DVM82A1FT00

Cell TypeNANDDensity256Mb
Access Time (max)35nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus25b
Operating Supply Voltage (typ)3.3VOperating Temp Range0C to 70C
Package TypeTSOP-ISync/asyncAsynchronous
Operating Temperature ClassificationCommercialOperating Supply Voltage (min)2.7V
Operating Supply Voltage (max)3.6VWord Size8b
Number Of Words32MSupply Current30mA
MountingSurface MountPin Count48
Lead Free Status / Rohs StatusNot Compliant  
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TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
256-MBIT (32M × 8 BITS) CMOS NAND E
DESCRIPTION
The device is a 256-Mbit (276,824,064) bit NAND Electrically Erasable and Programmable Read-Only Memory
2
(NAND E
PROM) organized as 528 bytes × 32 pages × 2048 blocks. The device uses single power supply (2.7 V to 3.6
V for V
). The device has a 528-byte static register which allows program and read data to be transferred between
CC
the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block
unit (16 Kbytes + 512 bytes: 528 bytes x 32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell allay 528 × 64K × 8
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
Mode control
Serial input/output
Command control
Power supply
Vcc:
2.7V to 3.6V
Program/Erase Cycles 1E5 cycle (with ECC)
Access time
Cell array to register 25 µs max
Serial Read Cycle
50 ns min
Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
50 µA max.
Standby
Package
TSOP I 48-P-1220-0.50 (Weight:0.53g typ)
PIN ASSIGNMENT (TOP VIEW
NC
1
NC
2
NC
3
NC
4
NC
5
GND
6
RY
/
BY
7
RE
8
CE
9
NC
10
NC
11
V
12
CC
V
13
SS
NC
14
NC
15
CLE
16
ALE
17
WE
18
WP
19
NC
20
NC
21
NC
22
NC
23
NC
24
2
PROM
PINNAMES
NC
48
I/O1 to I/O8
NC
47
NC
46
CE
NC
45
I/O8
44
WE
I/O7
43
I/O6
42
RE
I/O5
41
NC
40
NC
CLE
39
NC
38
V
37
ALE
CC
V
36
SS
NC
35
WP
NC
34
NC
33
RY
/
BY
I/O4
32
I/O3
31
GND
I/O2
30
I/O1
29
V
CC
NC
28
NC
27
V
SS
NC
26
NC
25
TC58DVM82A1FT00
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground input
Power supply
Ground
2003-03-25 1/34

TC58DVM82A1FT00 Summary of contents

  • Page 1

    ... CLE 16 ALE PROM PINNAMES NC 48 I/ I/ CLE ALE I/O4 32 I/O3 31 GND I/ TC58DVM82A1FT00 I/O port Chip enable Write enable Read enable Command latch enable Address latch enable Write protect Ready/Busy Ground input Power supply Ground 2003-03-25 1/34 ...

  • Page 2

    ... Status register Address register Command register Control HV generator VALUE − 0.6~4.6 − 0.6~4.6 − 0.6 V~V CC − 55~150 PARAMETER CONDITION OUT TC58DVM82A1FT00 Column buffer Column decoder Data register Sense amp Memory cell array + 0 ≦ 4.6 V) 0.3 260 0~70 MIN MAX = 0 V  ...

  • Page 3

    ... OUT = cycle = cycle = cycle   V/V IH − − pin V OL TC58DVM82A1FT00 MIN TYP. MAX  2008 2048 MIN TYP. MAX 2.7 3.3 3.6  + 0.3 2 − 0.3 *  0.8 MIN TYP. MAX   ± 10   ±  ...

  • Page 4

    ... CE High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load PARAMETER TC58DVM82A1FT00 MIN MAX UNIT     ...

  • Page 5

    ... Refer to Application Note (12) toward the end of this document. is greater than or equal to 100 ns. If the delay CEH / BY signal stays Ready. ≥ 100 ns t CEH 527 A Busy 2.5 MIN    TC58DVM82A1FT00 pin → Busy signal is not output. A TYP. MAX UNIT µ s 200 1000  ...

  • Page 6

    ... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 to I/O8 Setup Time CLH ALH TC58DVM82A1FT00 Hold Time 2003-03-25 6/34 ...

  • Page 7

    ... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/ I/O8 Data Input Cycle Timing Diagram CLE ALS ALE A16 TC58DVM82A1FT00 ALH A17 to A24 : CLH 527 2003-03-25 7/34 ...

  • Page 8

    ... Serial Read Cycle Timing Diagram REA I/ Status Read Cycle Timing Diagram CLE t CLS I/ I/ 70H represents the hexadecimal number REH RHZ REA RHZ t CLS t CLH WHC CSTO t WHR 70H * TC58DVM82A1FT00 CHZ REA RHZ t CEA t CHZ RSTO RHZ Status output : 2003-03-25 8/34 ...

  • Page 9

    ... CLE t t CLS CLH ALH ALS ALE I/O1 00H I/O8 Column address Read Operation using 00H Command 255 ALH AR2 A16 A17toA24 ALH AR2 A16 A17toA24 TC58DVM82A1FT00 REA OUT OUT OUT OUT 527 : CHZ REA RHZ OUT OUT OUT 2003-03-25 9/34 ...

  • Page 10

    ... DS DH I/O1 50H to I/ Read Operation using 50H Command N: 0 to15 t t ALS ALH A16 A17toA24 Column address ALS ALH A16 A17toA24 Column address N * TC58DVM82A1FT00 t AR2 REA D D OUT OUT 256 + M 256 + AR2 REA D D OUT OUT 512 + M 512 + 2003-03-25 10/34 D ...

  • Page 11

    ... A16 A17toA24 00H/0 Column address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 01H A16 A17toA24 to I/O8 Column address Page t R address M Page M access Page t 256 + 256 + R address Page M access TC58DVM82A1FT00 527 Page access : 527 2.5 Page access : 2003-03-25 11/34 527 527 ...

  • Page 12

    ... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 50H A16 A17toA24 to I/O8 Column address Page t 512 + 512 + 512 + R address Page M access TC58DVM82A1FT00 2.5 527 512 513 527 00H Page access : 2003-03-25 12/34 ...

  • Page 13

    ... BY Setup command t ALH t ALS A17toA24 not input data while data is being output ALH WB D0H Erase Start command : not input data while data is being output TC58DVM82A1FT00 t PROG 10H 70H 527 BERASE Status 70H output Status Read Busy command 2003-03-25 13/ Status output ...

  • Page 14

    ... ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 90H to I/ CEA t t ALH ALEA t REAID 00 98H Address Maker code input TC58DVM82A1FT00 t REAID 75H Device code : 2003-03-25 14/34 ...

  • Page 15

    ... BY The output signal is used to indicate the operating condition of the device. The = L) during the Program, Erase and Read operations and will return to Ready state Busy state ( after completion of the operation. The output buffer for this signal is an open drain. TC58DVM82A1FT00 GND ...

  • Page 16

    ... Capacity = 528 bytes × 32 pages × 2048 blocks 8I/O I/O6 I/O5 I/O4 I/O3 I/ A14 A13 A12 A11 A10 A22 A21 A20 A19 A18 TC58DVM82A1FT00 I/O1 A0~A7: Column address A9~A24: Page address A0 A14~A24: Block address A9 A9~A13: NAND address in block A17 2003-03-25 16/34 ...

  • Page 17

    ... ALE Second Cycle Acceptable while Busy       D0   ALE * TC58DVM82A1FT00 V/Vcc HEX data bit assignment (Example) Serial data input: 80H I/ I/O1 I/O1~I/O8 Power L Data output Active High impedance Active High impedance Standby 2003-03-25 17/34 *1 ...

  • Page 18

    ... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). Cell array TC58DVM82A1FT00 WE in the third cycle (after the CE signal must stay 2003-03-25 18/34 ...

  • Page 19

    ... A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output Busy Busy (01H) n Sequential Read (2) 2.5 TC58DVM82A1FT00 Data output t R Busy (50H Sequential Read (3) 2003-03-25 19/34 ...

  • Page 20

    ... Device Device 2 3 Busy 70H Status on Device 1 Figure 6. Status Read timing application example pin signals from multiple devices are wired together as shown in the TC58DVM82A1FT00 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device Status on Device N ...

  • Page 21

    ... After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. D0 Erase Start command Busy TC58DVM82A1FT00 Pass 70 I/O Status Read Fail command RY / ...

  • Page 22

    ... The second FF (max 10 µ RST (max 6 µ RST command is invalid, but the third TC58DVM82A1FT00 Figure 8. 00 Figure 9. 00 (max 500 µ s) RST Figure 10. 00 Figure 11. I/O status: Pass/Fail → Pass Ready/Busy → Ready I/O status: Ready/Busy → Busy Figure 12. ( command is valid ...

  • Page 23

    ... Table 6. ID Codes read out by ID read command 90H I/O8 Maker code 1 Device code 0 t CEA t ALEA t REAID 00 98H Maker code and t refer to the AC Characteristics. REAID CEA ALEA Figure 13. ID Read timing I/O7 I/O6 I/O5 I/ TC58DVM82A1FT00 75H Device code I/O3 I/O2 I/O1 Hex Data 98H 75H 2003-03-25 23/34 ...

  • Page 24

    ... Programming cannot be executed. “10H” or “FFH” reaches 2.5 V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 recommends starting access after about CC FF Reset Figure 16. 10 For this operation the “FFH” command is needed. TC58DVM82A1FT00 Don’t care V IL 2003-03-25 24/34 ...

  • Page 25

    ... Read mode. In this case, data output starts automatically from address N and address input is unnecessary Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 (1) (2) Page 1 (3) Page 2 Page 15 Page 31 Figure 17. page programming within a block 70 Status Read command input Figure 18. TC58DVM82A1FT00 Data (32) Data register (2) (16) (3) (1) (32) 00 [A] Status Read Status output 2003-03-25 25/34 ...

  • Page 26

    ... Start point C area C area Add Start point B area A area Add DIN Start point C Area Add Start point B Area Figure 20. Example of How to Set the Pointer TC58DVM82A1FT00 n/2-1 n/2 n Pointer control Figure 19 Pointer control 50H Add Start point C area 00H Add Start point ...

  • Page 27

    ... This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value DIN Ready 1.5 µ s 1.0 µ 0.5 µ Ω TC58DVM82A1FT00 buffer consists of an open drain Busy 25°C = 100 Ω Ω Ω R 2003-03-25 27/ ...

  • Page 28

    ... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min TC58DVM82A1FT00 2003-03-25 28/34 ...

  • Page 29

    ... Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when Program operation CLE CE WE ALE I/O 80H Address input WE goes High in the third cycle. Figure 22. Address input Ignored Figure 23. TC58DVM82A1FT00 Ignored Data input 2003-03-25 29/34 ...

  • Page 30

    ... BY Hence the RE clock input must start after the address input. All 1s Data Pattern 2 All 1s Data Pattern 2 Figure 24. ess counter is incremented synchronously with the Figure 25. TC58DVM82A1FT00 All 1s Data Pattern 3 Data Pattern 3 RE clock in Read co mmand, the internal Address input 2003-03-25 30/34 ...

  • Page 31

    ... Valid (Good) Block Number 2008 Read Check : to verify the column address 517 Start Block Fail Read Check Pass Block No. = 2048 Yes End Figure 27 TC58DVM82A1FT00 TYP. MAX UNIT  2048 Block bytes of the first page in the block with FFh Bad Block * 1 2003-03-25 31/34 ...

  • Page 32

    ... Block Verify after Program → Retry (2) ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 28. TC58DVM82A1FT00 2003-03-25 32/34 ...

  • Page 33

    ... Package Dimensions Weight: 0.53g (typ.) TC58DVM82A1FT00 Unit : mm 2003-03-25 33/34 ...

  • Page 34

    ... The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. TC58DVM82A1FT00 030619EBA 2003-03-25 34/34 ...