TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 

Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory
(J3 v. D)
32, 64, 128, and 256 Mbit
Product Features
Architecture
— High-density symmetrical 128-Kbyte blocks
— 256 Mbit (256 blocks)
— 128 Mbit (128 blocks)
— 64 Mbit (64 blocks)
— 32 Mbit (32 blocks)
Performance
— 75 ns Initial Access Speed (128/64/32
-Mbit densities)
— 95 ns Initial Access Speed (256 Mbit only)
— 25 ns 8-word and 4-word Asynchronous
page-mode reads
— 32-Byte Write buffer
— 4 µs per Byte Effective programming time
System Voltage and Power
— V
= 2.7 V to 3.6 V
CC
— V
= 2.7 V to 3.6 V
CCQ
Packaging
— 56-Lead TSOP package (32, 64, 128 Mbit
only)
— 64-Ball Numonyx Easy BGA package (32,
42, 128 and 256 Mbit)
Security
— Enhanced security options for code
protection
— 128-bit Protection Register
— 64-bit Unique device identifier
— 64-bit User-programmable OTP cells
— Absolute protection with V
PEN
— Individual block locking
— Block erase/program lockout during power
transitions
Software
— Program and erase suspend support
— Flash Data Integrator (FDI), Common Flash
Interface (CFI) Compatible
Quality and Reliability
— Operating temperature:
-40 °C to +85 °C
— 100K Minimum erase cycles per block
— 0.13 µm ETOX™ VIII Process
Datasheet
= GND
308551-05
November 2007

TE28F640J3D75 Summary of contents

  • Page 1

    ... Individual block locking — Block erase/program lockout during power transitions Software — Program and erase suspend support — Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Quality and Reliability — Operating temperature: -40 °C to +85 °C — 100K Minimum erase cycles per block — ...

  • Page 2

    ... Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “ ...

  • Page 3

    ... Numonyx™ Embedded Flash Memory ( Contents 1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 6 1.3 Conventions ....................................................................................................... 7 2.0 Functional Overview .................................................................................................. 8 2.1 Block Diagram .................................................................................................. 10 2.2 Memory Map..................................................................................................... 11 3.0 Package Information ............................................................................................... 12 3.1 56-Lead TSOP Package (32, 64, 128 Mbit) ............................................................ 12 3.2 Easy BGA Package (32, 64, 128 and 256 Mbit) ...................................................... 13 4 ...

  • Page 4

    ... Query Structure Overview...................................................................................59 13.3 Block Status Register .........................................................................................60 13.4 CFI Query Identification String ............................................................................60 13.5 System Interface Information ..............................................................................61 13.6 Device Geometry Definition .................................................................................61 13.7 Primary-Vendor Specific Extended Query Table ......................................................62 A Additional Information.............................................................................................66 B Ordering Information ...............................................................................................67 Datasheet 4 Numonyx™ Embedded Flash Memory ( November 2007 308551-05 ...

  • Page 5

    ... Numonyx™ Embedded Flash Memory ( Revision History Date Revision Description July 2005 001 Initial release Changed Marketing name from 28FxxxJ3 Updated the following: • Table 18, “Command Bus Operations” on page 35 September 2005 002 • Section 9.2.2, “Read Status Register” on page 38 • ...

  • Page 6

    ... The Numonyx™ Embedded Flash Memory J3 Version D ( provides improved mainstream performance with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Intel* 0.13 µm ETOX™ VIII process technology. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the Numonyx™ Embedded Flash Memory ( device brings reliable, low-voltage capability (3 V read, program, and erase) with high speed, low-power operation. The Numonyx™ ...

  • Page 7

    ... Numonyx™ Embedded Flash Memory ( SR: Status Register SRD: Status Register Data WSM: Write State Machine ECR: Enhanced Configuration Register 1.3 Conventions h: Hexadecimal Affix k (noun): 1,000 M (noun): 1,000,000 Nibble 4 bits Byte: 8 bits Word: 16 bits Kword: 1,024 words Kb: 1,024 bits KB: 1,024 bytes Mb: ...

  • Page 8

    ... This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families ...

  • Page 9

    ... Numonyx™ Embedded Flash Memory ( Blocks are selectively and individually lockable in-system. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (using the Set Block Lock-Bit and Clear Block Lock-Bits commands). ...

  • Page 10

    ... Y-Decoder 0 21 64-Mbit Input Buffer 0 22 128-Mbit Address Latch X-Decoder Address Counter Figure 2: Numonyx™ Embedded Flash Memory ( Memory Block Diagram (256 Mbit) CE# A[23-A0] Datasheet Output Input Buffer Buffer Query Identifier Register Status Register Multiplexer Data Comparator Y-Gating 32-Mbit: Thirty-two ...

  • Page 11

    ... Numonyx™ Embedded Flash Memory ( 2.2 Memory Map Figure 3: Numonyx™ Embedded Flash Memory ( Memory Map A[24-0]: 256 Mbit A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit 1FFFFFF 128-Kbyte Block 1FE0000 0FFFFFF 128-Kbyte Block 0FE0000 07FFFFF 128-Kbyte Block 07E0000 03FFFFF 128-Kbyte Block ...

  • Page 12

    ... TSOP Dimension Table Parameter Symbol Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Datasheet 12 Numonyx™ Embedded Flash Memory ( See Note 2 See Notes 1 and Detail Millimeters Min ...

  • Page 13

    ... Numonyx™ Embedded Flash Memory ( Table 1: 56-Lead TSOP Dimension Table Parameter Symbol Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset 3.2 Easy BGA Package (32, 64, 128 and 256 Mbit) Figure 5: Easy BGA Mechanical Specifications Ball A1 Corner Top View - Plastic Backside ...

  • Page 14

    ... Corner to Ball A1 Distance Along D (32/64/128 Mb) Corner to Ball A1 Distance Along E (32/64/128 Mb) Notes: 1. For Daisy Chain Evaluation Unit information refer to the Numonyx Flash Memory Packaging Technology Web page at: www.Numonyx.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Numonyx Flash Memory Packaging Technology Web page at: www.Numonyx.com/design/packtech/index.htm Datasheet 14 Numonyx™ ...

  • Page 15

    ... A16 A17 A17 A16 D4 RFU D15 STS STS D15 D12 RFU RFU OE# OE# RFU D5 D6 D14 WE# WE# D14 D13 VSS D7 RFU RFU D7 Intel® Embedded Flash Memory ( Figure 6, Figure 7 and Figure VCC A13 VPEN RFU A14 CE0# A9 VSS A2 C RFU A15 ...

  • Page 16

    ... RFU A16 A17 A17 A16 D4 RFU D15 STS STS D15 D12 RFU RFU OE# OE# RFU D5 D6 D14 WE# WE# D14 D13 VSS D7 A24 A24 D7 Intel® Embedded Flash Memory ( VCC A13 VPEN RFU A14 CE# A9 VSS A2 C RFU A15 A12 A10 RFU ...

  • Page 17

    ... Input/ D[7:0] during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data Output is internally latched during write operations. November 2007 308551-05 Intel® Embedded Flash Memory (28FXXXJ3D) 56-Lead TSOP Standard Pinout Top View 32/64/128 Mbit Name and Function selects the upper die ...

  • Page 18

    ... ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. VPEN Input With V PEN CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when V ≤ VCC Power LKO Caution: Device operation at invalid Vcc voltages should not be attempted. ...

  • Page 19

    ... Supply Voltage Supply Voltage CCQ CCQ 5.3 Power Up/Down This section provides an overview of system level considerations with regards to the flash device. It includes a brief description of power-up, power-down and decoupling design considerations. November 2007 308551-05 Min , Ambient) –40 –65 –2.0 –2.0 –2.0 — ...

  • Page 20

    ... By holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high- impedance state. After return from reset, a certain amount of time is required before the flash device is able to perform normal operations ...

  • Page 21

    ... Numonyx™ Embedded Flash Memory ( 6.0 Electrical Characteristics 6.1 DC Current Specifications Table 7: DC Current Characteristics V CCQ V CC Symbol Parameter I Input and V Load Current LI PEN I Output Leakage Current LO 32, 64, 128 Mbit I V Standby Current CCS CC 32, 64, 128 Mbit I V Power-Down Current CCD ...

  • Page 22

    ... LKO 5. Includes all operational modes of the device including standby and power-up sequences 6. Input/Output signals can undershoot to -1.0v referenced to V duration of 2ns or less, the V CCQ 6.3 Capacitance Table 9: Numonyx™ Embedded Flash Memory ( Capacitance Symbol C Input Capacitance IN C Output Capacitance OUT Notes: 1. ...

  • Page 23

    ... Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash device’s data sheet, and is the address-to-data delay for subsequent page-mode reads. ...

  • Page 24

    ... Figure 17, “AC Input/Output Reference Waveform” on page 30 4. See Equivalent Testing Load Circuit” on page 30 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (t Datasheet 24 Numonyx™ Embedded Flash Memory ( (3) = 2.7 V–3.6 V and V CC Density 32 Mbit 64 Mbit 128 Mbit 256 Mbit ...

  • Page 25

    ... CE low is defined as the last edge of CE0, CE1, or CE2 that enables the device CE0, CE1, or CE2 that disables the device. 2. When reading the flash array a faster t query reads, or device identifier reads). Figure 12: 4-Word Asynchronous Page Mode Read Waveform A[MAX:3] [A] A[2:1] [A] CEx [E] ...

  • Page 26

    ... CEx [E] OE# [G] WE# [W] D[15:0] [Q] RP# [P] BYTE# Notes low is defined as the last edge of CE0, CE1, or CE2 that enables the device CE0, CE1, or CE2 that disables the device this diagram, BYTE# is asserted high Datasheet 26 Numonyx™ Embedded Flash Memory ( R10 R7 R15 R10 R8 R9 ...

  • Page 27

    ... Numonyx™ Embedded Flash Memory ( 7.2 Write Specifications Table 11: Write Operations # Symbol RP# High Recovery to WE# (CE PHWL PHEL (WE#) Low to WE# (CE ELWL WLEL Write Pulse Width Data Setup to WE# (CE DVWH DVEH Address Setup to WE# (CE AVWH AVEH (WE#) Hold from WE# (CE WHEH EHWH Data Hold from WE# (CE ...

  • Page 28

    ... Figure 14: Asynchronous Write Waveform ADDRESS [A] CEx (WE#) [E (W)] WE# (CEx) [W (E)] OE# [G] DATA [D/Q] STS[R] W1 RP# [P] VPEN [V] Figure 15: Asynchronous Write to Read Waveform Address [A] CE# [E] WE# [W] OE# [G] Data [D/Q] W1 RST #/ RP# [P] VPEN [V] Datasheet 28 Numonyx™ Embedded Flash Memory ( W11 W11 W13 W8 W6 W12 ...

  • Page 29

    ... Numonyx™ Embedded Flash Memory ( 7.3 Program, Erase, Block-Lock Specifications Table 12: Configuration Performance # Symbol Write Buffer Byte Program Time W16 (Time to Program 32 bytes/16 words) t WHQV3 W16 Byte Program Time (Using Word/Byte Program Command) t EHQV3 Block Program Time (Using Write to Buffer Command) ...

  • Page 30

    ... L Figure 19: Test Configuration Test Configuration CCQ CCQMIN Datasheet 30 Numonyx™ Embedded Flash Memory ( Parameter , this specification is not applicable) CC Test Points for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at Device Under Test Min Max ...

  • Page 31

    ... Read, Program (Write), and Erase.The on-chip Write State Machine (WSM) manages all erase and program algorithms. The system CPU provides control of all in-system read, write, and erase operations through the system bus. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. ...

  • Page 32

    ... Asynchronous Page mode is the default read mode on power-up or reset. To perform a Page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous Page mode reads are permitted in all blocks and are used to access register information. During register access, only one word is loaded into the page buffer ...

  • Page 33

    ... Identifier codes, inspection, and clearing of the Status Register • Block Erasure, Program, and Lock-bit Configuration (when V Erasing is performed on a block basis – all flash cells within a block are erased together. Any information or data previously stored in the block will be lost. Erasing is typically done prior to programming ...

  • Page 34

    ... Confirm command. However, some commands are single-cycle commands consisting of a setup command only. Generally, commands that alter the contents of the flash device, such as Program or Erase, require at least two write cycles to guard against inadvertent changes to the flash device. Flash commands fall into two categories: Basic Commands and Extended Commands ...

  • Page 35

    ... Numonyx™ Embedded Flash Memory ( Table 18: Command Bus Operations Command Program Enhanced Configuration Register Program OTP Register Clear Status Register Program STS Configuration Register Read Array Read Status Register Read Identifier Codes (Read Device Information) CFI Query Word/Byte Program Buffered Program ...

  • Page 36

    ... Flash Operations This section describes the operational features of flash memory. Operations are command-based, wherein command codes are first issued to the device, then the device performs the desired operation. All command codes are issued to the device using bus-write cycles. A complete list of available command codes can be found in Section 10.0, “ ...

  • Page 37

    ... Numonyx™ Embedded Flash Memory ( 9.1.1 Clearing the Status Register The Status Register (SR) contain status and error bits which are set by the device. SR status bits are cleared by the device, however SR error bits are cleared by issuing the Clear Status Register command. Resetting the device also clears the Status Register. ...

  • Page 38

    ... The Read Device Information command functions independent of the voltage level on VPEN. 9.2.4 CFI Query The query table contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications, and other product information. The data contained in this table conforms to the Common Flash Interface (CFI) protocol. ...

  • Page 39

    ... WSM continues to run as normal but, user may advertently change the content in unexpected address locations. Note: User-data is programmed into the flash array at the address issued when filling the write buffer. After all user-data is written into the write buffer, issue the confirm command command other than the confirm command is issued to the device, a command sequence error occurs and the operation aborts ...

  • Page 40

    ... Note: After issuing the confirm command, write-buffer contents are programmed into the flash memory array. The Status Register indicates a busy status (SR7 = 0) during array programming.Issuing the Read Array command to the device while it is actively programming or erasing causes subsequent reads from the device to output invalid data ...

  • Page 41

    ... Numonyx™ Embedded Flash Memory ( Standby power levels are not be realized until the block-erase operation has finished. Also, asserting RP# aborts the block-erase operation, and array contents at the addressed location are indeterminate. The addressed block should be erased before programming within the block is attempted. ...

  • Page 42

    ... For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00 configuration code with the Configuration command resets the STS signal to the default RY/BY# level mode. Datasheet 42 Numonyx™ Embedded Flash Memory ( Program Suspend Not Allowed Allowed Not Allowed ...

  • Page 43

    ... Controls HOLD to a memory controller to prevent accessing a flash memory subsystem ready indication while any flash device's WSM is busy. Generates a system interrupt pulse when any flash device in an array has completed pulse on Erase Complete block erase. Helpful for reformatting blocks after file system free space reclamation or “ ...

  • Page 44

    ... Configurable Block Locking One of the unique new features on the Numonyx™ Embedded Flash Memory (J3 v. D), non-existent on the previous generations of this product family, is the ability to protect and/or secure the user’s system by offering multiple level of securities: Non-Volatile Temporary ...

  • Page 45

    ... Numonyx™ Embedded Flash Memory ( 9.7.6 Locking the OTP Protection Register The user-programmable segment of the Protection Register is lockable by programming Bit 1 of the Protection Lock Register (PLR Bit 0 of this location is programmed the Numonyx factory to protect the unique device number. Bit 1 is set using the Protection Program command to program “ ...

  • Page 46

    ... When it’s necessary to protect the entire array, global protection can be achieved using a hardware mechanism. using VPP or VPEN. Whenever a valid voltage is present on VPP or VPEN, blocks within the main flash array can be erased or programmed. By grounding VPP or VPEN, blocks within the main array cannot be altered – attempts to program or erase blocks will fail resulting in the setting of the appropriate error bit in the Status Register ...

  • Page 47

    ... Numonyx™ Embedded Flash Memory ( 10.0 Device Command Codes The list of all applicable commands are included here one more time for the convenience. Table 30: Command Bus Operations for Numonyx™ Embedded Flash Memory ( Command Program Enhanced Configuration Register Program OTP Register Clear Status Register ...

  • Page 48

    ... Device ID Codes Table 31: Read Identifier Codes Code Device Code Datasheet 48 Numonyx™ Embedded Flash Memory ( Address 32-Mbit 00001 64-Mbit 00001 128-Mbit 00001 256- Mbit 00001 Data 0016 0017 0018 001D November 2007 308551-05 ...

  • Page 49

    ... Numonyx™ Embedded Flash Memory ( 12.0 Flow Charts Figure 21: Write to Buffer Flowchart November 2007 308551-05 Start Setup - Write 0xE8 - Block Address Check Buffer Status - Perform read operation - Read Ready Status on signal SR7 No SR7 = 1? Yes Word Count - Address = block address - Data = word count minus 1 ...

  • Page 50

    ... See Suspend/Resume Flowchart Program Suspend SR2 = '1' See Suspend/Resume Flowchart SR5 = '1' SR4 = ' Error Erase Failure Y es Error SR4 = '1' Program Failure Error SR3 = '1' V < V PEN PENLK Error SR1 = '1' Block Locked No End Numonyx™ Embedded Flash Memory ( Error Command Sequence November 2007 308551-05 ...

  • Page 51

    ... Numonyx™ Embedded Flash Memory ( Figure 23: Byte/Word Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register 0 SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error ...

  • Page 52

    ... Start Write B0H Read Status Register SR SR Write FFH Read Data Array Done Reading Yes Write D0H Programming Resumed Datasheet 52 Numonyx™ Embedded Flash Memory ( Bus Operation Write Read Standby Standby 0 Write Read 0 Programming Completed Write No Write FFH Read Array Data ...

  • Page 53

    ... Numonyx™ Embedded Flash Memory ( Figure 25: Block Erase Flowchart Start Issue Single Block Erase Command 20H, Block Address Write Confirm D0H Block Address Read Status Register 0 SR Full Status Check if Desired Erase Flash Block(s) Complete November 2007 308551-05 Bus Operation Write ...

  • Page 54

    ... Read Status Register SR SR Read Read or Program? Read Array No Data Done? Yes Write D0H Block Erase Resumed Datasheet 54 Numonyx™ Embedded Flash Memory ( Bus Operation Write Read Standby Standby 0 Write 0 Block Erase Completed Program Program Loop Write FFH Read Array Data ...

  • Page 55

    ... Numonyx™ Embedded Flash Memory ( Figure 27: Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = ...

  • Page 56

    ... Data (See Above SR.4 SR Clear Block Lock-Bits Successful Datasheet 56 Numonyx™ Embedded Flash Memory ( Bus Operation Write Write Read Standby Write FFH after the clear lock-bits operation to place device in read array mode. Bus Operation Standby Voltage Range Error Standby Command Sequence ...

  • Page 57

    ... Numonyx™ Embedded Flash Memory ( Figure 29: Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register No SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above ...

  • Page 58

    ... Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI ...

  • Page 59

    ... Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. ...

  • Page 60

    ... Offset 15 defines “P” which points to the Primary Numonyx-Specific Extended Query Table. 13.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 35: Block Status Register Offset ...

  • Page 61

    ... Device Geometry Definition This field provides critical details of the flash device geometry. Table 38: Device Geometry Definition Offset Length 27h 1 “n” such that device size = 2 ...

  • Page 62

    ... Primary-Vendor Specific Extended Query Table Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 40: Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (Optional Flash Features and Commands) ...

  • Page 63

    ... Numonyx™ Embedded Flash Memory ( Table 40: Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (Optional Flash Features and Commands) Optional feature and command support (1=yes, 0=no) Undefined bits are “0.” If bit 31 is “1” then another 31 bit field of optional features follows at the end of the bit-30 field ...

  • Page 64

    ... Bits [27:10 Bits [30:28] = Memory type: • 000b = CSD Flash • 100b = LD Flash bit 31 = Another CFI link field immediately follows Datasheet 64 Numonyx™ Embedded Flash Memory ( Description (Optional Flash Features and Commands factory pre-programmed bytes n = user-programmable bytes Description (Optional Flash Features and Commands) ...

  • Page 65

    ... Numonyx™ Embedded Flash Memory ( Table 43: Additional CFI link for the lower die of the stacked device (256 Mb only) (1) Offset Length P = 31h (Optional Flash Features and Commands) CFI Link Quantity Subfield Definition Bits [3:0] = Quantity field (n such that n+1 equals quantity Bit 4 = Table & die relative location • ...

  • Page 66

    ... Call the Numonyx Literature Center at (800) 548-4725 to request Numonyx documentation. International customers should contact their local Numonyx or distribution sales office. 2. Visit the Numonyx home page 3. For the most current information on Numonyx™ Embedded Flash Memory (J3 v. D), visit developer.Numonyx.com/design/flash/isf. Datasheet 66 Numonyx™ Embedded Flash Memory ( Document/Tool http://www ...

  • Page 67

    ... Package TE= 56-Lead TSOP (J3C, 803 Pb-Free 56-TSOP RC = 64-Ball Easy BGA PC = 64-Ball Pb-Free Easy BGA Product line designator For all Intel® Flash Products Device Density 128 = x8/x16 (128 Mbit) 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Table 44: Valid Combinations for Discrete Family ...

  • Page 68

    ... C 4 Package Designator RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free Group Designator 48F = Flash Memory only Flash Density die 3 = 128-Mbit Product Family J = Intel® Embedded Flash Memory die Table 45: Valid Line Item Combinations for SCSP Family 256-Mbit RC48F3300J0Z00S PC48F3300J0Z00S Datasheet ...