TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Table 3:
Signal Descriptions for Numonyx™ Embedded Flash Memory (J3 v. D) (Sheet 2
of 2)
Symbol
Type
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Input/
D[15:8]
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
Output
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
CHIP ENABLE: Activate the 32-, 64- and 128 Mbit devices’ control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected, power reduces to standby levels.
CE[2:0]
Input
All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of
CE0, CE1, or CE2 that disables the device.
CHIP ENABLE: Activates the 256Mbit devices’ control logic, input buffers, decoders, and sense
amplifiers.
CE#
Input
Device selection occurs with the first edge of CE# that enables the device. Device deselection
occurs with the first edge of CE# that disables the device.s
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
RP#
Input
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE#
Input
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
WE#
Input
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
Open Drain
STS
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
Output
indicate program and/or erase completion. STS is to be tied to VCCQ with a pull-up resistor.
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
BYTE#
Input
the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order
address bit.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
VPEN
Input
With V
PEN
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when V
≤ V
.
VCC
Power
LKO
Caution: Device operation at invalid Vcc voltages should not be attempted.
VCCQ
Power
I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to V
GND
Supply
Ground: Ground reference for device logic voltages. Connect to system ground.
NC
No Connect: Lead is not internally connected; it may be driven or floated.
Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device
RFU
functionality and enhancement.
Datasheet
18
Numonyx™ Embedded Flash Memory (J3 v. D)
Name and Function
≤ V
, memory contents cannot be altered.
PENLK
CC
.
CC
November 2007
308551-05