TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 27

• Manufacturer Part Number: TE28F640J3D75
• Manufacturer: Intel

Specifications of TE28F640J3D75

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 75ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3/3.3V
• Sync/async: Asynchronous
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4Mword
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

Numonyx™ Embedded Flash Memory (J3 v. D)
7.2
Table 11: Write Operations
November 2007
308551-05
Notes:
CE
ables the device.
1.
2.
3.
4.
5.
6.
7.
8.
9.
W11
W12
W13
W15
W1
W2
W3
W4
W5
W6
W7
W8
W9
#
X
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
A write operation can be initiated and terminated with either CE
Sampled, not 100% tested.
Write pulse width (t
(whichever goes high first). Hence, t
Refer to
program, or lock-bit configuration.
Write pulse width high (t
low (whichever goes low first). Hence, t
For array access, t
STS timings are based on STS configured in its RY/BY# default mode.
V
= 0).
t
t
t
t
t
t
t
t
t
t
WHEH
DVWH
WHDX
AVWH
WHAX
WHGL
VPWH
WHRL
PEN
PHWL
ELWL
Symbol
t
t
should be held at V
QVVL
t
WPH
WP
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
EHWH
PHEL
DVEH
AVEH
EHDX
EHAX
VPEH
EHGL
EHRL
Table 16, “Enhanced Configuration Register” on page 33
Write Specifications
)
)
)
)
)
)
)
)
)
)
RP# High Recovery to WE# (CE
CE
Write Pulse Width
Data Setup to WE# (CE
Address Setup to WE# (CE
CE
Data Hold from WE# (CE
Address Hold from WE# (CE
Write Pulse Width High
V
Write Recovery before Read
WE# (CE
V
PEN
PEN
AVQV
X
X
WP
(WE#) Low to WE# (CE
(WE#) Hold from WE# (CE
Setup to WE# (CE
Hold from Valid SRD, STS Going High
) is defined from CE
is required in addition to t
PENH
WPH
X
) High to STS Going Low
) is defined from CE
until determination of block erase, program, or lock-bit configuration success (SR[1,3,4,5]
Parameter
WP
WPH
= t
X
X
) Going High
) Going High
X
X
WLWH
) High
X
or WE# going low (whichever goes low last) to CE
= t
) Going High
X
X
) Going Low
) High
WHWL
X
X
= t
X
) High
WHGL
) Going Low
or WE# going high (whichever goes high first) to CE
ELEH
= t
for any accesses after a write.
EHEL
= t
WLEH
= t
X
WHEL
= t
128 Mbit
Density
X
32 Mbit
64 Mbit
or WE#.
high is defined at the first edge of CE0, CE1, or CE2 that dis-
ELWH
All
= t
EHWL
.
.
Min
150
180
210
60
50
55
30
35
Valid for All
0
0
0
0
0
0
for valid A
Speeds
Max
500
IN
X
and D
or WE# going high
IN
Unit
X
for block erase,
ns
or WE# going
Datasheet
1,2,3,8,9
Notes
1,2,3
1,2,4
1,2,4
1,2,5
1,2,5
1,2,6
1,2,3
1,2,8
1,2,7
1,2,
1,2,
1,2,
27