TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
7.2
Write Specifications
Table 11: Write Operations
#
Symbol
W1
t
(t
)
RP# High Recovery to WE# (CE
PHWL
PHEL
W2
t
(t
)
CE
(WE#) Low to WE# (CE
ELWL
WLEL
X
W3
t
Write Pulse Width
WP
W4
t
(t
)
Data Setup to WE# (CE
DVWH
DVEH
W5
t
(t
)
Address Setup to WE# (CE
AVWH
AVEH
W6
t
(t
)
CE
(WE#) Hold from WE# (CE
WHEH
EHWH
X
W7
t
(t
)
Data Hold from WE# (CE
WHDX
EHDX
W8
t
(t
)
Address Hold from WE# (CE
WHAX
EHAX
W9
t
Write Pulse Width High
WPH
W11
t
(t
)
V
Setup to WE# (CE
VPWH
VPEH
PEN
W12
t
(t
)
Write Recovery before Read
WHGL
EHGL
W13
t
(t
)
WE# (CE
) High to STS Going Low
WHRL
EHRL
X
W15
t
V
Hold from Valid SRD, STS Going High
QVVL
PEN
Notes:
CE
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
X
ables the device.
1.
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
2.
A write operation can be initiated and terminated with either CE
3.
Sampled, not 100% tested.
4.
Write pulse width (t
) is defined from CE
WP
(whichever goes high first). Hence, t
Table 16, “Enhanced Configuration Register” on page 33
5.
Refer to
program, or lock-bit configuration.
6.
Write pulse width high (t
) is defined from CE
WPH
low (whichever goes low first). Hence, t
7.
For array access, t
is required in addition to t
AVQV
8.
STS timings are based on STS configured in its RY/BY# default mode.
9.
V
should be held at V
until determination of block erase, program, or lock-bit configuration success (SR[1,3,4,5]
PEN
PENH
= 0).
November 2007
308551-05
Parameter
Density
32 Mbit
) Going Low
64 Mbit
X
128 Mbit
) Going Low
X
) Going High
X
) Going High
X
) High
X
) High
X
All
) High
X
) Going High
X
high is defined at the first edge of CE0, CE1, or CE2 that dis-
X
or WE#.
X
or WE# going low (whichever goes low last) to CE
X
= t
= t
= t
= t
.
WP
WLWH
ELEH
WLEH
ELWH
or WE# going high (whichever goes high first) to CE
X
= t
= t
= t
= t
WPH
WHWL
EHEL
WHEL
EHWL
for any accesses after a write.
WHGL
Valid for All
Speeds
Unit
Notes
Min
Max
150
1,2,3
180
210
0
1,2,4
60
1,2,4
50
1,2,5
55
1,2,5
0
ns
1,2,
0
1,2,
0
1,2,
30
1,2,6
0
1,2,3
35
1,2,7
500
1,2,8
0
1,2,3,8,9
or WE# going high
X
for valid A
and D
for block erase,
IN
IN
or WE# going
X
.
Datasheet
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