TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
8.0
Bus Interface
This section provides an overview of Bus operations. Basically, there are three operations you can
do with flash memory: Read, Program (Write), and Erase.The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of all in-system read,
write, and erase operations through the system bus. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
states of each control signal for different modes of operations.
Table 14: Bus Operations
Mode
Async., Status, Query and Identifier
Reads
Output Disable
Standby
Reset/Power-down
Command Writes
(8)
Array Writes
Notes:
Table 15
1.
See
for valid CE
Configurations.
x
2.
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
3.
DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high.
4.
Refer to DC characteristics. When V
5.
X should be V
or V
for the control pins and V
IL
IH
6.
In default mode, STS is V
when the WSM is executing internal block erase, program, or a lock-bit configuration
OL
algorithm. It is V
(pulled up by an external pull up resistance ~= 10k) when the WSM is not busy, in block erase
OH
suspend mode (with programming inactive), program suspend mode, or reset power-down mode.
Table 18, “Command Bus Operations” on page 35
7.
See
operation
8.
Array writes are either program or erase operations. /
Table 15: Chip Enable Truth Table
CE2
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
Note:
For single-chip applications, CE2 and CE1 can be connected to
The next few sections detail each of the basic flash operations and some of the
advanced features available on flash memory.
November 2007
308551-05
Table 14
(1)
(2)
(2)
RP#
CE
OE#
WE#
x
V
Enabled
V
V
IH
IL
IH
V
Enabled
V
V
IH
IH
IH
Disable
V
X
X
IH
d
V
X
X
X
IL
V
Enabled
V
V
IH
IH
IL
V
Enabled
V
V
IH
IH
IL
V
, memory contents can be read but not altered.
PEN
PENLK
or V
for V
. For outputs, X should be V
PENLK
PENH
PEN
for valid DIN (user commands) during a Write
CE1
CE0
V
V
IL
IL
V
V
IL
IH
V
V
IH
IL
V
V
IH
IH
V
V
IL
IL
V
V
IL
IH
V
V
IH
IL
V
V
IH
IH
.
GND
summarizes the necessary
STS
(
DQ
15:0
V
(Default
Notes
3)
PEN
Mode)
X
D
High Z
OUT
X
High Z
High Z
X
High Z
High Z
X
High Z
High Z
X
D
High Z
IN
V
X
V
PENH
IL
or V
.
OL
OH
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
Datasheet
4,6
6,7
8,5
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